Abstract:
An organic light emitting display device includes a driving transistor having one electrode connected with a node, and another electrode connected with an organic light emitting element, a first control transistor for receiving a first driving voltage through one electrode, and having another electrode connected with the node, a second control transistor for receiving a second driving voltage through one electrode, and having another electrode connected with the node, and a sensing transistor having one electrode connected between the another electrode of the driving transistor and the organic light emitting element, wherein the sensing transistor is turned on in a sensing period, the first control transistor is turned off in the sensing period, and the second control transistor is turned on in the sensing period.
Abstract:
An input sensing device includes a first base layer, a plurality of first sensing electrodes, a plurality of second sensing electrodes, a plurality of third sensing electrodes, and a plurality of fourth sensing electrodes. The first sensing electrodes are arranged on the first base layer along a first direction. The second sensing electrodes are arranged on the first base layer in different rows from the first sensing electrodes. The third sensing electrodes are arranged on the second sensing electrodes along a second direction different from the first direction. The third sensing electrodes overlap the second sensing electrodes. The fourth sensing electrodes are arranged on the same layer as the third sensing electrodes and overlap the first sensing electrodes. A constant voltage is applied to the third sensing electrodes during a touch pressure sensing operation.
Abstract:
There is provided a stage circuit capable of minimizing a mounting area. The stage circuit includes: an output unit configured to supply a voltage of a first node, an i-th (i is a natural number) carry signal, and to supply an i-th scan signal in response to the voltage of the first node, a voltage of a second node, and a first clock signal, a controller configured to control the voltage of the second node in response to the first clock signal; a pull-up unit configured to control the voltage of the first node in response to a carry signal of a previous stage and a voltage of a first node of the previous stage, and a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and a carry signal of a next stage.
Abstract:
A gate driving circuit includes: a plurality of stages configured to output a plurality of gate signals, wherein an Nth stage of the plurality of stages includes: an output pull-up unit including a control electrode connected to a first node, wherein the output pull-up unit is configured to increase an electric potential at the first node and is further configured to receive a clock signal and to output a gate signal of the Nth stage; a control node pull-up unit configured to charge the first node according to an (N−1)th control signal and an (N−2)th control signal; a control node pull-down unit configured to discharge a voltage of the first node as a first low voltage according to an (N+1)th control signal; and an output pull-down unit configured to discharge a gate signal of the Nth stage as the first low voltage according to the (N+1)th control signal.
Abstract:
A liquid crystal display including: a first substrate; a gate line and a data line formed or otherwise disposed on the first substrate; a drain electrode disposed on the first substrate; a first insulating layer disposed on the gate line and the data line; a first electrode disposed on the first insulating layer; a second insulating layer disposed on the first electrode; and a second electrode disposed on the second insulating layer. The first insulating layer and the second insulating layer have a first contact hole exposing a portion of the drain electrode. The contact portion of the second electrode is connected to the drain electrode through the first contact hole, and the contact portion overlaps the first electrode adjacent the first contact hole. The overlap increases capacitance of the display panel so as to decrease kickback voltage and reduce flicker.
Abstract:
A liquid crystal display includes: a first substrate; a reference voltage line including a storage electrode; a pixel electrode including a first subpixel electrode and a second subpixel electrode, and disposed in a pixel area; a second substrate facing the first substrate; and a liquid crystal layer provided between the first substrate and the second substrate, wherein the first subpixel electrode includes a first horizontal stem and a first vertical stem, the second subpixel electrode includes a second horizontal stem and a second vertical stem, the second subpixel electrode is provided to an external side of the pixel area to surround the first subpixel electrode, and the storage electrode includes a first storage electrode overlapping the first horizontal stem of the first subpixel electrode, and a second storage electrode overlapping the second vertical stem of the second subpixel electrodes.
Abstract:
A display device that may compensate for characteristic deviations among pixels and impact picture quality is provided. The display device includes a plurality of pixels, a plurality of sensing lines connected to the pixels, a sensing circuit configured to extract characteristic information of the pixels through the sensing lines. The sensing circuit includes a plurality of analog-to-digital converters (ADC) to convert the characteristic information into digital sensing data and to output the digital sensing data. A compensating circuit is configured to compare output values of the plurality of ADCs, to set a correction value, and to convert first data into second data based on the sensing data and the correction value. A data driver is configured to generate data signals corresponding to the second data and to output the data signals to the pixels.
Abstract:
A scan driver includes a plurality of stages configured to supply scan signals to scan lines. An ith (i is a natural number) stage of the stages at one side of a panel includes: a first transistor connected between a first input terminal and a first node, and including a gate electrode connected to a second input terminal; a second transistor connected between a third input terminal and a first output terminal for outputting an ith scan signal of the scan signals, and including a gate electrode connected to the first node; a third transistor connected between the first output terminal and a first power input terminal configured to receive a first off voltage, and including a gate electrode connected to the second input terminal; and a first capacitor connected between the first node and the first output terminal.
Abstract:
A display panel includes a gate line extending in a column direction, a data line extending in a row direction, a pixel including a switching transistor connected to the gate line and the data line, and a voltage applier connected to a gate line of a present stage. The voltage applier to apply a voltage after conversion of the gate-on voltage to a gate-off voltage has started. The voltage is closer to the gate-on voltage than the gate-off voltage.
Abstract:
A thin film transistor array panel including a first substrate, a gate conductor on the first substrate, a data conductor on the gate conductor, a shielding electrode on the data conductor and insulated from the data conductor, a passivation layer on the shielding electrode, and a pixel electrode on the passivation layer, in which the shielding electrode includes a vertical portion vertically extending along an edge of a pixel area and overlapped with the data line, and one or more horizontal portions connecting the vertical portions.