公开(公告)号：US20240186392A1

公开(公告)日：2024-06-06

申请号：US18062116

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin PARK ,  Myung Gil Kang ,  Dong Won Kim ,  Keun Hwi Cho

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/775

Abstract: A semiconductor device including a substrate, a first and second active pattern extending in a first horizontal direction on the substrate, the second active pattern apart from the first active pattern in the first horizontal direction, first nanosheets apart from each other in a vertical direction on the first active pattern, second nanosheets apart from each other in the vertical direction on the first and second active patterns, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the first active pattern and surrounding the first nanosheets, a source/drain region between the first and second nanosheets, an active cut penetrating the second nanosheets in the vertical direction, extending to the substrate, and separating the first and second active patterns, and a sacrificial layer between the source/drain region and the active cut, in contact with the active cut, and including silicon germanium may be provided.

公开(公告)号：US11990534B2

公开(公告)日：2024-05-21

申请号：US17886612

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Minyi Kim ,  Keun Hwi Cho

IPC: H01L29/732 ,  H01L21/8228 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/732 ,  H01L21/82285 ,  H01L21/823821 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/735

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

公开(公告)号：US11978805B2

公开(公告)日：2024-05-07

申请号：US18110961

申请日：2023-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78645 ,  H01L29/66484 ,  H01L29/6675 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/78696

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US11843000B2

公开(公告)日：2023-12-12

申请号：US17336785

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin Park ,  Myung Gil Kang ,  Dong Won Kim ,  Keun Hwi Cho

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/02603 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOI substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.

公开(公告)号：US11824059B2

公开(公告)日：2023-11-21

申请号：US17369236

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi Cho ,  Sangdeok Kwon ,  Dae Sin Kim ,  Dongwon Kim ,  Yonghee Park ,  Hagju Cho

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/82385 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L2027/11829 ,  H01L2027/11851 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US20230163131A1

公开(公告)日：2023-05-25

申请号：US18157591

申请日：2023-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoung-Sun Lee ,  Keun Hwi Cho

IPC: H01L27/092 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L27/0207 ,  H01L21/823814

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

公开(公告)号：US11387345B2

公开(公告)日：2022-07-12

申请号：US17176226

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il An ,  Keun Hwi Cho ,  Dae Won Ha ,  Seung Seok Ha

IPC: H01L29/51 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L49/02

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US11063065B2

公开(公告)日：2021-07-13

申请号：US16454532

申请日：2019-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Guk Il An ,  Keun Hwi Cho ,  Sung Min Kim ,  Yoon Moon Park

IPC: H01L27/1159 ,  H01L27/11592

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first interfacial layer disposed on the substrate in the first region and having a first thickness; a second interfacial layer disposed on the substrate in the second region, wherein the second interfacial layer includes a second thickness that is smaller than the first thickness; a first gate insulating layer disposed on the first interfacial layer and including a first ferroelectric material layer; a second gate insulating layer disposed on the second interfacial layer; a first gate electrode disposed on the first gate insulating layer; and a second gate electrode disposed on the second gate insulating layer.

公开(公告)号：US11004981B2

公开(公告)日：2021-05-11

申请号：US16504960

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US10957373B2

公开(公告)日：2021-03-23

申请号：US16428184

申请日：2019-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun Hwi Cho ,  Seunghan Park ,  Hyo-Jin Kim ,  Gukil An

IPC: G11C11/22 ,  H01L29/51 ,  H01L27/11502

Abstract: A semiconductor memory device includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, write drivers and sense amplifiers connected to the memory cell array through second conductive lines, a voltage generator that supplies a first voltage to the row decoder and supplies a second voltage to the write drivers and sense amplifiers, and a data buffer that is connected to the write drivers and sense amplifiers and transfers data between the write drivers and sense amplifiers and an external device. At least one of the row decoder, the write drivers and sense amplifiers, the voltage generator, and the data buffer includes a first ferroelectric capacitor to amplify a voltage.