公开(公告)号：US20210125983A1

公开(公告)日：2021-04-29

申请号：US16946060

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dahye Kim ,  Jaemun Kim ,  Jinbum Kim ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66

Abstract: Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.

公开(公告)号：US10043800B2

公开(公告)日：2018-08-07

申请号：US15442859

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhwa Kim ,  Kyungin Choi ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66

Abstract: An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.

公开(公告)号：US09941174B2

公开(公告)日：2018-04-10

申请号：US15007711

申请日：2016-01-27

Applicant: Samsung Electronics Co., Ltd

Inventor： Kyungin Choi ,  Ah-Young Cheon ,  Kwang-Yong Yang ,  Myungil Kang ,  Dohyoung Kim ,  YoonHae Kim

IPC: H01L31/0312 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66545

Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

公开(公告)号：US09577075B2

公开(公告)日：2017-02-21

申请号：US14460404

申请日：2014-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Sunghyun Choi ,  Yong-Suk Tak ,  Bonyoung Koo ,  Jaejong Han

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/223 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

Abstract translation: 一种制造半导体器件的方法包括形成在第一方向上延伸的预备鳍型有源图案，形成覆盖预备鳍型有源图案的下部的器件隔离图案，形成沿第二方向延伸的栅极结构，以及 跨越预备鳍型有源图案，形成具有第一区域和第二区域的鳍式有源图案，通过选择性外延生长工艺在第二区域上形成预备杂质掺杂图案，并形成杂质 通过使用等离子体掺杂工艺注入杂质的掺杂图案，其中第一区域的上表面处于第一水平，并且第二区域的上表面处于低于第一水平的第二水平。

公开(公告)号：US20160365274A1

公开(公告)日：2016-12-15

申请号：US15145924

申请日：2016-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Jaeran Jang ,  Yoonhae Kim

IPC: H01L21/768 ,  H01L29/08 ,  H01L29/16 ,  H01L27/11 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L21/76825 ,  H01L21/31155 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.

Abstract translation: 制造半导体器件的方法包括在衬底上形成栅极图案，形成间隔物以覆盖栅极图案的两个侧壁，形成层间绝缘层以覆盖栅极图案和间隔物，并形成穿透层间绝缘层的接触孔 并暴露间隔物的侧壁。 间隔件的形成包括形成间隔层以覆盖栅极图案并将硅离子注入间隔层。 间隔层是介电常数低于氧化硅的介电常数的氮化物基低k绝缘层。