公开(公告)号：US20220328408A1

公开(公告)日：2022-10-13

申请号：US17532052

申请日：2021-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho Do ,  Sanghoon Baek

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.

公开(公告)号：US11302636B2

公开(公告)日：2022-04-12

申请号：US16946491

申请日：2020-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoung Lee ,  Sanghoon Baek

IPC: H01L23/528 ,  H01L23/522 ,  G06F30/392 ,  G06F30/3953

Abstract: A semiconductor device includes: a device layer including first and second active patterns, extending in a first direction on a substrate and adjacent to each other, and a plurality of gate electrodes extending in a second direction, intersecting the first direction, on the substrate and crossing the first and second active patterns; a lower wiring layer on the device layer, and including first and second lower wiring patterns extending in the first direction, located on the first and second active patterns, respectively, and connected to the plurality of gate electrodes; and an upper wiring layer on the lower wiring layer, and having first and second upper vias on the first and second lower wiring patterns, respectively, and first and second upper wiring patterns extending in the second direction. The first upper wiring pattern is connected to the first upper via without being connected to the second upper via and the second upper wiring pattern is connected to the second upper via without being connected to the first upper via.

公开(公告)号：US10242984B2

公开(公告)日：2019-03-26

申请号：US15614911

申请日：2017-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Sutae Kim ,  Donghyun Kim ,  Ha-Young Kim ,  Jung-ho Do ,  Sunyoung Park ,  Sanghoon Baek ,  Jaewan Choi

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

公开(公告)号：US10037401B2

公开(公告)日：2018-07-31

申请号：US15896415

申请日：2018-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong Song ,  Sanghoon Baek ,  Sungwe Cho ,  Jung-Ho Do ,  Giyoung Yang ,  Jinyoung Lim

IPC: G06F17/50 ,  H01L27/118 ,  H01L27/02

CPC classification number: G06F17/5077 ,  H01L27/0207 ,  H01L27/11807

Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

公开(公告)号：US10026688B2

公开(公告)日：2018-07-17

申请号：US15692670

申请日：2017-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoung Lee ,  Sanghoon Baek ,  Jung-Ho Do

IPC: H01L21/4763 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.

公开(公告)号：US09929023B2

公开(公告)日：2018-03-27

申请号：US15350716

申请日：2016-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Jonghoon Jung ,  Sanghoon Baek ,  Seungyoung Lee ,  Taejoong Song ,  Jinyoung Lim

IPC: H01L21/8238 ,  H01L21/3213

CPC classification number: H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878

Abstract: A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.

公开(公告)号：US09887210B2

公开(公告)日：2018-02-06

申请号：US15238912

申请日：2016-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong Song ,  Ha-Young Kim ,  Jung-Ho Do ,  Sanghoon Baek ,  Jinyoung Lim ,  Kwangok Jeong

IPC: H01L21/76 ,  H01L27/118 ,  G06F17/50 ,  G03F1/36 ,  H01L21/8238 ,  H01L21/66 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US09496179B2

公开(公告)日：2016-11-15

申请号：US14833922

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sunyoung Park ,  Sang-Kyu Oh ,  Jintae Kim ,  Hyosig Won

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/321

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/41758 ,  H01L29/66568

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.

Abstract translation: 一种制造半导体器件的方法包括：在基板上形成与有源图案交叉的有源图案和栅电极，在栅电极侧形成连接到有源图案的第一触点，形成连接到栅电极的第二触点 并且形成在栅电极侧与第一接触连接的第三触点。 使用不同于用于形成第一接触的光掩模形成第三接触。 第三触点的底表面设置在低于第一触点的顶表面的高度的装置中的水平面上。