公开(公告)号：US4593307A

公开(公告)日：1986-06-03

申请号：US509732

申请日：1983-06-30

Applicant: Hans S. Rupprecht ,  Sandip Tiwari

Inventor： Hans S. Rupprecht ,  Sandip Tiwari

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/285 ,  H01L29/45 ,  H01L23/48

CPC classification number: H01L21/28575 ,  H01L29/452 ,  Y10S148/084 ,  Y10S148/14

Abstract: This invention relates generally to ohmic contacts to substrates made of III-V compounds and to a process for fabricating such contacts. More specifically, the invention is directed to a contact to gallium arsenide having a given level of n-type dopant therein, a region of the substrate doped with germanium and a layer of a germanide of a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum disposed on the substrate. Still more specifically, the invention relates to an ohmic contact to gallium arsenide which includes an interface region of germanium heavily doped with arsenic disposed between the region doped with germanium and the layer of germanide. The contact is formed by evaporating germanium and a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum on the surface of an n-type gallium arsenide substrate and sintering the substrate in a reducing atmosphere for a time and at a temperature sufficient to form the first-to-form germanide of the refractory metal. The resulting contact is stable, has a very low contact resistance and may be subjected to later high temperature processing steps without affecting its characteristics.

Abstract translation: 本发明一般涉及由III-V化合物制成的衬底的欧姆接触以及制造这种接触的方法。 更具体地，本发明涉及其中具有给定水平的n型掺杂剂的砷化镓的接触，掺杂有锗的衬底的区域和选自钼， 设置在基板上的钨和钽。 更具体地，本发明涉及对砷化镓的欧姆接触，其包括重掺杂砷的锗的界面区域，其设置在掺杂有锗的区域和锗化物层之间。 接触是通过在n型砷化镓衬底的表面上蒸发锗和选自钼，钨和钽的难熔金属形成的，并在还原气氛中烧结衬底一段时间并在足以 形成难熔金属的第一个到形式的锗化物。 所得到的接触是稳定的，具有非常低的接触电阻并且可以经受稍后的高温处理步骤而不影响其特性。

公开(公告)号：US20140007308A1

公开(公告)日：2014-01-02

申请号：US13539778

申请日：2012-07-02

Applicant: Mark C. Reuter ,  Brian A. Bryce ,  Bojan R. Ilic ,  Sandip Tiwari

Inventor： Mark C. Reuter ,  Brian A. Bryce ,  Bojan R. Ilic ,  Sandip Tiwari

IPC: G01Q70/08 ,  G01Q60/38

CPC classification number: G01Q70/10 ,  B82Y15/00 ,  G01Q70/12

Abstract: A probe for scanned probe microscopy is provided. The probe includes a cantilever beam and a tip. The cantilever beam extends along a generally horizontal axis. The cantilever beam has a crystal facet surface that is oriented at a tilt angle with respect to the generally horizontal axis. The tip projects outwardly from the crystal facet surface.

Abstract translation: 提供扫描探针显微镜探针。 探头包括悬臂梁和尖端。 悬臂梁沿着大致水平的轴线延伸。 悬臂梁具有相对于大致水平轴线倾斜倾斜的晶面表面。 尖端从晶面表面向外突出。

公开(公告)号：US08080839B2

公开(公告)日：2011-12-20

申请号：US12549906

申请日：2009-08-28

Applicant: Sandip Tiwari ,  Moon-Kyung Kim ,  Joshua Mark Rubin ,  Soo-Doo Chae ,  Choong-Man Lee ,  Ravishankar Sundararaman

Inventor： Sandip Tiwari ,  Moon-Kyung Kim ,  Joshua Mark Rubin ,  Soo-Doo Chae ,  Choong-Man Lee ,  Ravishankar Sundararaman

IPC: H01L29/84

CPC classification number: H01L49/00 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00

Abstract: An electro-mechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.

Abstract translation: 机电晶体管包括彼此间隔开的源电极和漏电极。 源极柱位于衬底和源电极之间。 漏极柱位于衬底和漏电极之间。 可移动通道与源电极和漏电极间隔开。 门纳米柱位于可移动通道和基板之间。 第一电介质层位于可移动沟道和栅极纳米柱之间。 第二电介质层位于源极柱和源极之间。 第三介电层位于漏极柱和漏极之间。

公开(公告)号：US07365398B2

公开(公告)日：2008-04-29

申请号：US11055014

申请日：2005-02-11

Applicant: Sandip Tiwari ,  Arvind Kumar

Inventor： Sandip Tiwari ,  Arvind Kumar

IPC: H01L29/76 ,  G11C11/00

CPC classification number: H01L27/1104 ,  H01L27/11

Abstract: A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

Abstract translation: 高密度形式的静态随机存取存储器（SRAM）利用了硅两面的晶体管栅极和通过绝缘体上硅和三维集成的复杂形式实现的高互连性。 这种技术允许通过利用两侧的门的放置，在3D中形成常见的接触和密集的互连，从而非常紧凑地形成p沟道和n沟道器件。

公开(公告)号：US07057234B2

公开(公告)日：2006-06-06

申请号：US10462386

申请日：2003-06-16

Applicant: Sandip Tiwari

Inventor： Sandip Tiwari

IPC: H01L27/01

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/76254 ,  H01L27/10 ,  H01L29/66825

Abstract: According to an aspect of the invention, a device structure is provided where charging and discharging occur in a trapping region formed by a stack of films that is placed on the back of a thin silicon channel. Uncoupling the charging mechanisms that lead to the memory function from the front gate transistor operation allows efficient scaling of the front gate. But significantly more important is a unique character of these devices: these structures can be operated both as a transistor and as a memory. The thin active silicon channel and the thin front oxide provide the capability of scaling the structure to tens of nanometers, and the dual function of the device is obtained by using two voltage ranges that are clearly distinct. At small voltages the structure operates as a normal transistor, and at higher voltages the structure operates as a memory device.

Abstract translation: 根据本发明的一个方面，提供一种器件结构，其中充电和放电发生在由放置在薄硅通道的背面上的一叠薄膜形成的捕获区域中。 从前门晶体管操作中解除导致存储功能的充电机制允许前门的高效缩放。 但是，更重要的是这些器件的独特特性：这些结构可以作为晶体管和存储器运行。 薄的有源硅沟道和薄的前部氧化物提供了将结构缩放到几十纳米的能力，并且通过使用明显不同的两个电压范围来获得器件的双重功能。 在小电压下，结构作为正常晶体管工作，在较高电压下，该结构作为存储器件运行。

公开(公告)号：US20050224994A1

公开(公告)日：2005-10-13

申请号：US11055014

申请日：2005-02-11

Applicant: Sandip Tiwari ,  Arvind Kumar

Inventor： Sandip Tiwari ,  Arvind Kumar

IPC: H01L21/8244 ,  H01L27/11 ,  H01L31/062

CPC classification number: H01L27/1104 ,  H01L27/11

Abstract: A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

Abstract translation: 高密度形式的静态随机存取存储器（SRAM）利用了硅两面的晶体管栅极和通过绝缘体上硅和三维集成的复杂形式实现的高互连性。 这种技术允许通过利用两侧的门的放置，在3D中形成常见的接触和密集的互连，从而非常紧凑地形成p沟道和n沟道器件。

公开(公告)号：US06800518B2

公开(公告)日：2004-10-05

申请号：US10334220

申请日：2002-12-30

Applicant: Robert E. Bendernagel ,  Kwang Su Choe ,  Bijan Davari ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

Inventor： Robert E. Bendernagel ,  Kwang Su Choe ,  Bijan Davari ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC: H01L318234

CPC classification number: H01L21/324 ,  H01L21/76243

Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structure are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.

Abstract translation: 提供了图案化的SOI / SON复合结构及其形成方法。 在SOI / SON复合结构中，图案化SOI / SON结构夹在Si上层和半导体衬底之间。 形成图案化SOI / SON复合结构的方法包括共同的处理步骤，其中SOI和SON结构形成在一起。 本发明还提供一种形成复合结构的方法，该复合结构包括掩埋导电/ SON结构以及形成仅包括掩埋空隙平面的复合结构的方法。

公开(公告)号：US06756257B2

公开(公告)日：2004-06-29

申请号：US09975435

申请日：2001-10-11

Applicant: Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

Inventor： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC: H01L2100

CPC classification number: H01L27/10894 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76286 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/945 ,  Y10S257/904

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

Abstract translation: 描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑 如CMOS。 氧离子注入用于在所选择的深度形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。 可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。 本发明克服了形成DRAM的存储电容器形成的体积为Si的深沟槽，同时在SOI上形成合并的逻辑区域的问题。

公开(公告)号：US06600173B2

公开(公告)日：2003-07-29

申请号：US09943099

申请日：2001-08-30

Applicant: Sandip Tiwari

Inventor： Sandip Tiwari

IPC: H01L2904

CPC classification number: H01L27/11 ,  H01L21/76254 ,  H01L21/76838 ,  H01L21/76898 ,  H01L21/7806 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/1104 ,  H01L2225/06513 ,  H01L2924/0002 ,  Y10S977/712 ,  Y10S977/896 ,  Y10S977/936 ,  H01L2924/00

Abstract: In a method for forming a three dimensional interconnected structure, sets of devices on receiver and donor semiconductor substrates. The donor substrate is implanted with two or more exfoliating implants, the substrates are bonded together to form a bonded structure that is heated until a portion of the donor substrate exfoliates from the bonded structure and leaves a residual portion of the donor bonded to the receiver. To form three dimensional interconnected integrated circuits from devices formed on donor and receiver substrates, the receiver devices are covered with a protective and bonding layer. Interconnect structures extending from the surface of the protective and bonding layer to the devices of the receiver are formed, and a donor is implanted with two or more exfoliating implants. After bonding and heating of the two substrates until a portion of the donor exfoliates from the bonded substrates, leaving a remaining layer of the donor bonded to the receiver, the resulting devices are interconnected in an integrated circuit.

公开(公告)号：US06472705B1

公开(公告)日：2002-10-29

申请号：US09195083

申请日：1998-11-18

Applicant: Donald Stimson Bethune ,  Sandip Tiwari

Inventor： Donald Stimson Bethune ,  Sandip Tiwari

IPC: H01L3524

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0014 ,  G11C23/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0046 ,  H01L51/0541 ,  H01L51/0545 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/943

Abstract: The present invention is directed to a microelectric device and especially a Field effect transistor comprising a source, drain, channel, an insulating layer overlying said channel containing at least one closed cage molecule, said closed cage molecule being capable of exhibiting a Coulomb blockade effect upon application of a voltage between said source and drain. Two different microelectronic devices are described containing the closed cage molecule, a logic cell and a memory cell.

Abstract translation: 本发明涉及一种微电子器件，特别是一种场效应晶体管，其包括源极，漏极，沟道，覆盖所述沟道的绝缘层，所述绝缘层包含至少一个闭合笼状分子，所述封闭笼分子能够表现出库仑阻塞效应 在所述源极和漏极之间施加电压。 描述了包含封闭笼分子，逻辑单元和存储单元的两种不同的微电子器件。