公开(公告)号：US20240233847A1

公开(公告)日：2024-07-11

申请号：US18357274

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Xiaochen Zhu ,  Lito De La Rama

IPC: G11C29/02 ,  G11C29/52

CPC classification number: G11C29/021 ,  G11C29/022 ,  G11C29/52

Abstract: A non-volatile memory system detects a memory operation failure. In response to the memory operation failure, the system determines whether adjusting an overdrive voltage applied to a word line avoids the memory operation failure. If adjusting the overdrive voltage applied to the word line avoids the memory operation failure, then future memory operations are performed by applying the adjusted overdrive voltage to the word line.

公开(公告)号：US11972812B2

公开(公告)日：2024-04-30

申请号：US17549431

申请日：2021-12-13

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Jun Wan ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two criteria, the memory system performs some amount of programming on the memory cells to refresh the data stored in those memory cells to be as originally intended.

公开(公告)号：US11955184B2

公开(公告)日：2024-04-09

申请号：US17740429

申请日：2022-05-10

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiaochen Zhu ,  Xiang Yang ,  Lito De La Rama ,  Yi Song ,  Jiahui Yuan

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/28 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.

公开(公告)号：US11894071B2

公开(公告)日：2024-02-06

申请号：US17549457

申请日：2021-12-13

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Dengtao Zhao ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/28 ,  G11C16/10 ,  G11C7/04 ,  G11C16/26

CPC classification number: G11C16/28 ,  G11C7/04 ,  G11C16/10 ,  G11C16/26

Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

公开(公告)号：US20230420051A1

公开(公告)日：2023-12-28

申请号：US17847831

申请日：2022-06-23

Applicant: SanDisk Technologies LLC

Inventor： Xue Qing Cai ,  Henry Chin ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/32 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/32 ,  G11C11/5628 ,  G11C16/26

Abstract: A method for multi-stage programming of a non-volatile memory structure, wherein the method comprises: (1) initiating a programming operation with respect to a memory block, (2) applying a programming algorithm to the memory block, wherein the programming algorithm comprises at least a first programming stage and a second programming stage, and (3) between the first programming stage and the second programming stage, applying a time delay according to a pre-determined amount of time. Further, the pre-determined amount of time may be defined as the amount of time that, according to a probabilistic function, permits de-trapping of any charges unintentionally trapped within a memory cell of the memory block as a result of the first programming stage.

公开(公告)号：US20230410911A1

公开(公告)日：2023-12-21

申请号：US17825321

申请日：2022-05-26

Applicant: SanDisk Technologies LLC

Inventor： Towhidur Razzak ,  Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L25/0657 ,  G11C16/3459 ,  G11C16/08

Abstract: Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc during verify to a target peak Icc regardless of which word line is selected for verify. However, the ramp rate of the voltages to the word lines during verify is fast enough to make use of the target peak Icc in order achieve faster programming. Therefore, the impact on programming time is minimized while staying withing the allowed peak Icc.

公开(公告)号：US20230410906A1

公开(公告)日：2023-12-21

申请号：US17824143

申请日：2022-05-25

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Xiang Yang

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/28 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08

Abstract: An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation to program data memory cells. The control circuit is configured to apply a second dummy word line voltage to the one or more dummy word lines in a read operation to read the data memory cells.

公开(公告)号：US20230395157A1

公开(公告)日：2023-12-07

申请号：US17832441

申请日：2022-06-03

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Yanjie Wang

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10

Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.

公开(公告)号：US11791001B2

公开(公告)日：2023-10-17

申请号：US17699508

申请日：2022-03-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Dengtao Zhao

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/28 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/28 ,  G11C16/3404

Abstract: A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.

公开(公告)号：US20230223084A1

公开(公告)日：2023-07-13

申请号：US17571124

申请日：2022-01-07

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Fanqi Wu ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C7/10

CPC classification number: G11C16/102 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C7/1048

Abstract: A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.