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    Nanowire FET and FINFET Hybrid Technology
    41.
    发明申请
    Nanowire FET and FINFET Hybrid Technology 失效
    纳米线FET和FINFET混合技术

    公开(公告)号：US20130105897A1

    公开(公告)日：2013-05-02

    申请号：US13286311

    申请日：2011-11-01

    申请人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

    IPC分类号： H01L27/12 ,  H01L21/8238

    CPC分类号： H01L27/1211 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3247 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/78696

    摘要： Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.

    摘要翻译： 提供了混合纳米线FET和FinFET器件及其制造方法。 一方面，制造具有纳米线FET和finFET的CMOS电路的方法包括以下步骤。 提供了在BOX上具有活性层的晶片。 有源层的第一区域变薄。 有机平面化层沉积在有源层上。 使用第一硬掩模在有源层的第一区域中蚀刻纳米线和焊盘。 纳米线悬挂在BOX上。 使用第二硬掩模在活性层的第二区域中蚀刻金箔。 形成围绕每个纳米线的至少一部分的第一栅极堆叠。 形成第二栅极堆叠，覆盖每个散热片的至少一部分。 在纳米线，焊盘和鳍片的暴露部分上生长外延材料。

    Nanowire FET with trapezoid gate structure
    42.
    发明授权
    Nanowire FET with trapezoid gate structure 有权
    具有梯形栅极结构的纳米线FET

    公开(公告)号：US08298881B2

    公开(公告)日：2012-10-30

    申请号：US12824293

    申请日：2010-06-28

    申请人： Jeffrey W. Sleight ,  Sarunya Bangsaruntip ,  Sebastian U. Engelmann ,  Ying Zhang

    发明人： Jeffrey W. Sleight ,  Sarunya Bangsaruntip ,  Sebastian U. Engelmann ,  Ying Zhang

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/4232 ,  H01L29/513 ,  H01L29/66439

    摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.

    摘要翻译： 在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。 该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。 与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。 梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。 然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源区和漏区。

    Interconnection between sublithographic-pitched structures and lithographic-pitched structures
    43.
    发明授权
    Interconnection between sublithographic-pitched structures and lithographic-pitched structures 有权
    亚光刻凹凸结构与平版印刷结构之间的互连

    公开(公告)号：US08247904B2

    公开(公告)日：2012-08-21

    申请号：US12540759

    申请日：2009-08-13

    申请人： Sarunya Bangsaruntip ,  Daniel C. Edelstein ,  William D. Hinsberg ,  Ho-Cheol Kim ,  Steven Koester ,  Paul M. Soloman

    发明人： Sarunya Bangsaruntip ,  Daniel C. Edelstein ,  William D. Hinsberg ,  Ho-Cheol Kim ,  Steven Koester ,  Paul M. Soloman

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76816 ,  H01L21/31144 ,  H01L21/76838 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different.

    摘要翻译： 形成了亚光刻间距结构和光刻凸出结构之间的互连。 具有亚光刻间距的多条导线可以被光刻图案化并且沿着与多根导线的长度方向成小于45度的角度的切割。 或者，与均聚物混合的共聚物可以放置在凹陷区域中并自对准以形成在恒定宽度区域具有亚光刻间距的多条导线，以及在梯形区域处的相邻线之间的光刻尺寸。 或者，具有亚光刻间距的第一多个导线和具有光刻间距的第二多个导线可以形成在相同的水平或不同的位置。

    DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS
    45.
    发明申请
    DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS 失效
    不同厚度的氧化硅纳米线场效应晶体管

    公开(公告)号：US20110133280A1

    公开(公告)日：2011-06-09

    申请号：US12631148

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Andres Bryant ,  Guy M. Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Andres Bryant ,  Guy M. Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/78696 ,  H01L29/42392

    摘要： A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.

    摘要翻译： 产生结构的方法（图案）至少形成两条半导体材料线，使得电线的第一线具有比电线的第二线更大的周长。 该方法在导线上同时进行氧化处理，以在第一布线上形成第一栅极氧化物，在第二布线上形成第二栅极氧化物。 第一栅极氧化物比第二栅极氧化物厚。 该方法还在第一栅极氧化物和第二栅极氧化物上形成栅极导体，在栅极导体上形成侧壁间隔物，以及第一导线和第二导线的掺杂部分未被侧壁间隔物和栅极导体覆盖以形成源极和 第一线和第二线内的漏极区。

    SELF-ALIGNED CONTACTS FOR NANOWIRE FIELD EFFECT TRANSISTORS
    46.
    发明申请
    SELF-ALIGNED CONTACTS FOR NANOWIRE FIELD EFFECT TRANSISTORS 有权
    用于纳米效应晶体管的自对准接触

    公开(公告)号：US20110133165A1

    公开(公告)日：2011-06-09

    申请号：US12631213

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L29/66 ,  H01L21/336

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.

    摘要翻译： 形成纳米线场效应晶体管（FET）器件的方法包括在半导体衬底上形成纳米线，在纳米线的一部分周围形成栅极结构，在栅极结构上形成覆盖层; 形成邻近所述栅极的侧壁和从所述栅极延伸的纳米线的周围的第一间隔物，在所述覆盖层和所述第一间隔物上形成硬掩模层，去除所述纳米线的暴露部分，在暴露的横截面上外延生长掺杂半导体材料 以形成源极区和漏极区，在外延生长的掺杂半导体材料中形成硅化物材料，并在源极和漏极区上形成导电材料。

    Nanowire field-effect transistors
    47.
    发明授权
    Nanowire field-effect transistors 有权
    纳米线场效应晶体管

    公开(公告)号：US07795677B2

    公开(公告)日：2010-09-14

    申请号：US11850608

    申请日：2007-09-05

    申请人： Sarunya Bangsaruntip ,  Guy Moshe Cohen ,  Katherine Lynn Saenger

    发明人： Sarunya Bangsaruntip ,  Guy Moshe Cohen ,  Katherine Lynn Saenger

    IPC分类号： H01L29/72

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/22 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/784 ,  Y10S977/938

    摘要： Field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a FET is provided. The FET comprises a substrate having a silicon-on-insulator (SOI) layer which is divided into at least two sections electrically isolated from one another, one section included in a source region and the other section included in a drain region; a channel region connecting the source region and the drain region and including at least one nanowire; an epitaxial semiconductor material, grown from the SOI layer, covering the nanowire and attaching the nanowire to each section of the SOI layer; and a gate over the channel region.

    摘要翻译： 提供具有纳米线通道的场效应晶体管（FET）。 一方面，提供了FET。 FET包括具有绝缘体上硅（SOI）层的衬底，其被划分成彼此电隔离的至少两个部分，一个部分包括在源极区域中，另一个部分包括在漏极区域中; 连接源极区域和漏极区域并且包括至少一个纳米线的沟道区域; 从SOI层生长的外延半导体材料，覆盖纳米线并将纳米线附接到SOI层的每个部分; 和通道区域上的门。

    Sensing of biological molecules using carbon nanotubes as optical labels
    48.
    发明申请
    Sensing of biological molecules using carbon nanotubes as optical labels 审中-公开
    使用碳纳米管作为光学标签感测生物分子

    公开(公告)号：US20090166560A1

    公开(公告)日：2009-07-02

    申请号：US11977550

    申请日：2007-10-24

    申请人： Hongjie Dai ,  Sarunya Bangsaruntip ,  Nozomi Nakayama

    发明人： Hongjie Dai ,  Sarunya Bangsaruntip ,  Nozomi Nakayama

    IPC分类号： G21G5/00 ,  G01J3/44 ,  G01N33/566

    CPC分类号： G01N33/54373 ,  B82Y5/00 ,  B82Y15/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/152 ,  C01B32/174 ,  C01B2202/02 ,  C01B2202/04 ,  C01B2202/06 ,  C01B2202/28 ,  G01N33/54346

    摘要： Disclosed are methods and materials including carbon nanotubes which have a strong Raman and/or fluorescent signal and which have been modified with an amphiphilic molecule having available functional linking groups for linking to a biological compound. Exemplified are surface-functionalized SWNTs (single walled nanotubes) as highly sensitive bio-labels based on the detection of their spectroscopic Raman signature. By solubilizing the nanotubes with polyethylene glycol (PEG)-containing phospholipids, aqueous-stable as well as biocompatible SWNT labels are produced. Specificity in biological detection is then attained by immobilizing reporting molecules off this PEG layer. Highly selective detection of surface immobilized proteins is achieved with detection limit of ˜10 femtomolar, three orders of magnitude higher than the fluorescent technique. Signal stability upon Raman readout as well as compatibility of the SWNT-tagged proteins to the microarray protocols are also demonstrated, making these biocompatible SWNTs highly attractive as novel, alternative bio-labels for ultrasensitive detection of proteins. When excited with a near infrared laser, the nanoparticles give off a distinctive fluorescence signal.

    摘要翻译： 公开了包括具有强拉曼和/或荧光信号的碳纳米管的方法和材料，其已经用具有用于连接到生物化合物的可用功能连接基团的两亲分子进行了修饰。 作为基于检测其光谱拉曼特征的高度敏感的生物标记物，表征为表面官能化的单壁碳纳米管（单壁纳米管）。 通过用含聚乙二醇（PEG）的磷脂使纳米管溶解，产生水稳定以及生物相容的SWNT标记。 然后通过将报告分子固定在该PEG层上来实现生物检测中的特异性。 表面固定化蛋白质的高度选择性检测是通过检测限达到10倍，而荧光技术高出3个数量级。 还证明了拉曼读数时的信号稳定性以及SWNT标记的蛋白质与微阵列方案的相容性，使得这些生物相容的SWNT作为用于蛋白质的超灵敏检测的新型替代生物标记物具有高度吸引力。 当用近红外激光激发时，纳米颗粒发出独特的荧光信号。

    Techniques for Fabricating Nanowire Field-Effect Transistors
    49.
    发明申请
    Techniques for Fabricating Nanowire Field-Effect Transistors 有权
    制造纳米线场效应晶体管的技术

    公开(公告)号：US20090061568A1

    公开(公告)日：2009-03-05

    申请号：US11850644

    申请日：2007-09-05

    申请人： Sarunya Bangsaruntip ,  Guy Moshe Cohen ,  Katherine Lynn Saenger

    发明人： Sarunya Bangsaruntip ,  Guy Moshe Cohen ,  Katherine Lynn Saenger

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66545 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696 ,  Y10S977/72 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/938

    摘要： Techniques for the fabrication of field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a method of fabricating a FET is provided comprising the following steps. A substrate is provided having a silicon-on-insulator (SOI) layer. At least one nanowire is deposited over the SOI layer. A sacrificial gate is formed over the SOI layer so as to cover a portion of the nanowire that forms a channel region. An epitaxial semiconductor material is selectively grown from the SOI layer that covers the nanowire and attaches the nanowire to the SOI layer in a source region and in a drain region. The sacrificial gate is removed. An oxide is formed that divides the SOI layer into at least two electrically isolated sections, one section included in the source region and the other section included in the drain region. A gate dielectric layer is formed over the channel region. A gate is formed over the channel region separated from the nanowire by the gate dielectric layer. A metal-semiconductor alloy is formed over the source and drain regions.

    摘要翻译： 提供了具有纳米线通道的场效应晶体管（FET）制造技术。 一方面，提供一种制造FET的方法，包括以下步骤。 提供了具有绝缘体上硅（SOI）层的衬底。 在SOI层上沉积至少一个纳米线。 牺牲栅极形成在SOI层上，以覆盖形成沟道区的纳米线的一部分。 从覆盖纳米线的SOI层选​​择性地生长外延半导体材料，并将纳米线附着在源极区域和漏极区域中的SOI层。 牺牲栅被去除。 形成氧化物，其将SOI层分成至少两个电隔离部分，一个部分包括在源极区域中，另一个部分包括在漏极区域中。 栅极电介质层形成在沟道区域上。 栅极形成在通过栅极介电层与纳米线分离的沟道区上。 在源极和漏极区域上形成金属 - 半导体合金。