公开(公告)号：US20240038619A1

公开(公告)日：2024-02-01

申请号：US17876621

申请日：2022-07-29

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Kwang-Soo Kim ,  Vivek Arora

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L24/83 ,  H01L24/32 ,  H01L21/4882 ,  H01L23/5389 ,  H01L23/3735 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/3512 ,  H01L2924/1711 ,  H01L2924/172 ,  H01L2924/173 ,  H01L2924/176 ,  H01L2924/1033 ,  H01L2224/83862 ,  H01L2224/3201 ,  H01L2224/83203

Abstract: An electronic device includes an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.

公开(公告)号：US11869839B2

公开(公告)日：2024-01-09

申请号：US17317873

申请日：2021-05-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Benjamin Allen Samples ,  Vivek Kishorechand Arora

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/532 ,  H01L25/07 ,  H01L49/02 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5226 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/53228 ,  H01L24/09 ,  H01L25/072 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381

Abstract: A packaged electronic device includes a semiconductor die with an electronic component and a contact structure connected to the electronic component, as well as an organic panel frame, a lamination structure that partially embeds the semiconductor die in an opening of the organic panel frame, and a ceramic substrate mounted to a first side of the semiconductor die.

公开(公告)号：US20230395514A1

公开(公告)日：2023-12-07

申请号：US17830291

申请日：2022-06-01

Applicant: Texas Instruments Incorporated

Inventor： Kwnag-Soo Kim ,  Vivek Kishorechand Arora ,  Woochan Kim

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/373

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L23/3735 ,  H01L21/481 ,  H01L23/3121

Abstract: An example semiconductor package comprises a multi-layer substrate having a bottom metal layer, a top metal layer, and a first insulation layer between bottom metal layer and the top metal layer. A plurality of first conductive traces are formed in the top metal layer. A second insulation layer is disposed over the exposed portions of the first insulation layer and over segments of the first conductive traces. A plurality of second conductive traces formed on top of the second insulation layer. One or more semiconductor dies are mounted on the one or more second segments of the conductive traces. One or more bond wires couple the semiconductor dies to one or more of the second conductive traces. A mold compound covers at least a portion of the semiconductor dies, the second insulation layer, the first conductive traces, and the second conductive traces.

公开(公告)号：US11329025B2

公开(公告)日：2022-05-10

申请号：US16828298

申请日：2020-03-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Arora ,  Woochan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56 ,  H01F27/40 ,  H01F27/06 ,  H01L25/00

Abstract: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

公开(公告)号：US11158595B2

公开(公告)日：2021-10-26

申请号：US16028741

申请日：2018-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/29 ,  H01L23/528 ,  H01L23/522 ,  H01L23/538 ,  H01L23/433 ,  H01L23/367

Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.

公开(公告)号：US20210305207A1

公开(公告)日：2021-09-30

申请号：US16828298

申请日：2020-03-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Arora ,  Woochan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495 ,  H01L25/00 ,  H01L21/56 ,  H01F27/40 ,  H01F27/06

Abstract: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

公开(公告)号：US11075147B2

公开(公告)日：2021-07-27

申请号：US16504816

申请日：2019-07-08

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Ken Pham

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/64 ,  H01L21/48

Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.

公开(公告)号：US11031332B2

公开(公告)日：2021-06-08

申请号：US16263110

申请日：2019-01-31

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Benjamin Allen Samples ,  Vivek Kishorechand Arora

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/538 ,  H01L23/532 ,  H01L25/07 ,  H01L49/02 ,  H01L23/00 ,  H01L25/00

Abstract: A packaged electronic device includes a semiconductor die with an electronic component and a contact structure connected to the electronic component, as well as an organic panel frame, a lamination structure that partially embeds the semiconductor die in an opening of the organic panel frame, and a ceramic substrate mounted to a first side of the semiconductor die.

公开(公告)号：US20210134729A1

公开(公告)日：2021-05-06

申请号：US16669666

申请日：2019-10-31

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

公开(公告)号：US20250087591A1

公开(公告)日：2025-03-13

申请号：US18960733

申请日：2024-11-26

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.