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公开(公告)号：US20100046283A1
公开(公告)日：2010-02-25
申请号：US12303821
申请日：2007-06-01
IPC分类号： G11C11/00 , G11C11/14 , G11C11/416
CPC分类号： G11C11/1673 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01L27/228
摘要： A magnetic random access memory of the present invention includes: a plurality of first wirings and a plurality of second wirings extending in a first direction; a plurality of third wirings and a plurality of fourth wirings extending in a second direction; and a plurality of memory cells provided at intersections of the plurality of first wirings and the plurality of third wirings, respectively. Each of the plurality of memory cells includes: a first transistor and a second transistor connected in series between one of the plurality of first wirings and one of the plurality of second wirings and controlled in response to a signal on one of the plurality of third wirings, a first magnetic resistance element having one end connected to a write wiring through which the first transistor and the second transistor are connected, and the other end grounded; and a second magnetic resistance element having one end connected to the write wiring, and the other end connected to the fourth wiring.
摘要翻译： 本发明的磁性随机存取存储器包括：沿第一方向延伸的多个第一布线和多条第二布线; 多个第三布线和沿第二方向延伸的多个第四布线; 以及多个存储单元，分别设置在所述多个第一布线和所述多个第三布线的交点处。 所述多个存储单元中的每一个包括：第一晶体管和第二晶体管，其串联连接在所述多个第一布线中的一个与所述多个第二布线中的一个之间，并响应于所述多个第三布线之一上的信号而被控制 第一磁阻元件，其一端连接到第一晶体管和第二晶体管连接的写入布线，另一端接地; 以及第二磁阻元件，其一端连接到写入布线，另一端连接到第四布线。
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公开(公告)号：US07630234B2
公开(公告)日：2009-12-08
申请号：US12066926
申请日：2006-09-07
IPC分类号： G11C11/14
CPC分类号： B82Y10/00 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693
摘要： An MRAM having a first cell array group (2-0)and a second cell array group (2-1) containing a plurality of cell arrays (21) is used. Each of the first cell array group (2-0) and the second cell array group (2-1) includes a first current source unit for supplying a first write current IWBL to a bit line WBL of the cell array (21) and a first current waveform shaping unit having a first capacitor requiring precharge and shaping the waveform of the first write current IWBL. When the cell array (21) performs write into a magnetic memory (24), the first current waveform shaping unit of the first cell array group (2-0) and the first current waveform shaping unit of the second cell array group (2-1) charges and discharges electric charge accumulated in the first capacitor to wiring toward the bit line WBL at different periods from each other.
摘要翻译： 使用具有包含多个单元阵列（21）的第一单元阵列组（2-0）和第二单元阵列组（2-1）的MRAM。 第一单元阵列组（2-0）和第二单元阵列组（2-1）中的每一个包括用于将第一写入电流IWBL提供给单元阵列（21）的位线WBL的第一电流源单元和 第一电流波形整形单元，其具有需要预充电的第一电容器并且对第一写入电流IWBL的波形进行整形。 当单元阵列（21）对磁存储器（24）进行写入时，第一单元阵列组（2-0）的第一电流波形整形单元和第二单元阵列组（2- 1）对在第一电容器中累积的电荷进行充电和放电，以不同的周期向位线WBL布线。
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公开(公告)号：US20090141544A1
公开(公告)日：2009-06-04
申请号：US12083692
申请日：2006-10-17
CPC分类号： G06F11/1044 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C2029/0411
摘要： An operation method of an MRAM of the present invention is an operation method of the MRAM in which a data write operation is carried out in a toggle write. The operation method of the present invention includes: (A) reading a data from a data cell by using a reference signal which is generated by using a reference cell; (B) performing an error detection on the read data; (C) correcting the data stored in the data cell, when an error is detected in the read data; (D) reading the data from the data cell as a first re-read data after the (C), when the error is detected in the read data, (E) performing the error detection on the first re-read data; (F) correcting the data stored in the reference cell, when an error is detected in the first re-read data; (G) reading the data from the data cell as a second re-read data after the (F), when the error is detected in the first re-read data; (H) performing the error detection on the second re-read data; and (I) correcting the data stored in the data cell again, when the error is detected in the second re-read data.
摘要翻译： 本发明的MRAM的操作方法是在切换写入中执行数据写入操作的MRAM的操作方法。 本发明的操作方法包括：（A）通过使用通过使用参考单元生成的参考信号从数据单元读取数据; （B）对所读取的数据执行错误检测; （C）当在读取数据中检测到错误时，校正存储在数据单元中的数据; （D）在（C）之后读取来自数据单元的数据作为第一重新读取数据，当在读取数据中检测到错误时，（E）对第一重新读取的数据执行错误检测; （F）当在所述第一重读数据中检测到错误时，校正存储在所述参考单元中的数据; （G）当在所述第一重新读取的数据中检测到所述错误时，读取来自所述数据单元的数据作为所述（F）之后的第二重新读取数据; （H）对所述第二再读数据执行所述错误检测; 以及（I）当在第二重新读取的数据中检测到错误时，再次校正存储在数据单元中的数据。
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公开(公告)号：US07492629B2
公开(公告)日：2009-02-17
申请号：US11614231
申请日：2006-12-21
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A semiconductor memory device is provided with a memory array including memory cells arranged in rows and columns; and a sense amplifier circuit. Each of the memory cells includes at least one magnetoresistive element storing data, and an amplifying member used to amplify a signal generated by a current through the at least one magnetoresistive element. The sense amplifier circuit identifies data stored in the at least one magnetoresistive element in response to an output signal of the amplifying member.
摘要翻译： 半导体存储器件设置有包括排列成行和列的存储单元的存储器阵列; 和读出放大器电路。 每个存储单元包括存储数据的至少一个磁阻元件和用于放大由通过至少一个磁阻元件的电流产生的信号的放大构件。 感测放大器电路响应于放大构件的输出信号识别存储在至少一个磁阻元件中的数据。
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公开(公告)号：US20080285360A1
公开(公告)日：2008-11-20
申请号：US11815325
申请日：2006-02-01
CPC分类号： G11C11/16 , G11C7/02 , G11C7/062 , G11C7/14 , G11C11/4091 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit.
摘要翻译： 本发明的半导体存储器件包括存储器阵列和读取所选择的单元的数据的读取电路。 存储器阵列包括多个存储器单元和参考单元，每个存储器单元具有存储元件，该存储元件基于电阻值的变化存储数据。 读取电路包括：电压比较单元，将来自所选择的单元的检测电流的值与来自参考单元的参考电流对应的值进行比较; 第一个开关 和第二开关。 第一和第二开关都被提供在解码器的后续阶段，并且在电压比较单元的前一级提供。 第二开关电路将对应于感测电流的值的输入控制到电压比较单元，而第一开关电路将对应于参考电流的值的输入控制到电压比较单元。
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公开(公告)号：US20070195585A1
公开(公告)日：2007-08-23
申请号：US10591617
申请日：2005-03-02
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A MRAM includes: first wirings, second wirings, memory cells, a second sense amplifier and a first sense amplifier. The first wirings and second wirings are extended in a first and a second direction. The memory cells are placed correspondingly to positions where the first wirings are crossed with the second wirings. The second sense amplifier detects a state of a reference cell on the basis of an output from the reference cell provided by corresponding to a reference wiring. The first sense amplifier (2) detects a state of the memory cell on the basis of an output from the reference cell and an output from the memory cell. The memory cell includes a magnetic tunneling junction element having a laminated free layer. The magnetic tunneling junction element has a magnetization easy axis direction which is different from the first and second directions.
摘要翻译： MRAM包括：第一布线，第二布线，存储单元，第二读出放大器和第一读出放大器。 第一布线和第二布线沿第一和第二方向延伸。 存储单元对应于第一配线与第二配线交叉的位置放置。 第二读出放大器基于对应于参考布线提供的参考单元的输出来检测参考单元的状态。 第一读出放大器（2）基于来自参考单元的输出和来自存储单元的输出来检测存储器单元的状态。 存储单元包括具有层叠自由层的磁性隧道接合元件。 磁性隧道接合元件具有不同于第一和第二方向的易磁化方向的磁化方向。
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公开(公告)号：US20060126377A1
公开(公告)日：2006-06-15
申请号：US10541645
申请日：2003-12-26
CPC分类号： G11C11/15
摘要： The present invention relates to a semiconductor memory device in which information is written into a storage element by flowing current. The invention aims at shortening write speed and reducing power consumption by preventing parasitic capacitors from prolonging the time required for a write current to reach a predetermined value. The apparatus includes storage elements for storing information, a constant current source for writing information into the storage element by flowing current, and a boost circuit for charging parasitic capacitors by a time when an amount of a current flowed by said constant current source reaches an amount of a current required to write information into the storage element, at a predetermined position related to the storage element.
摘要翻译： 本发明涉及通过流过电流将信息写入存储元件的半导体存储器件。 本发明旨在通过防止寄生电容器延长写入电流达到预定值所需的时间来缩短写入速度并降低功耗。 该装置包括用于存储信息的存储元件，用于通过流动电流将信息写入存储元件的恒定电流源和用于对由所述恒定电流源流过的电流量达到一定量的时间的寄生电容器充电的升压电路 在与存储元件相关的预定位置处需要将信息写入存储元件的电流。
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48.发明授权Magnetic random access memory including a cell array having a magneto-resistance element 失效磁性随机存取存储器包括具有磁阻元件的单元阵列公开(公告)号：US06885579B2
公开(公告)日：2005-04-26
申请号：US10609906
申请日：2003-07-01
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/15
摘要： In a magnetic random access memory, a cross point cell array of memory cells is arranged in a matrix of columns and rows, and each of the memory cells has a magneto-resistance element. A column of dummy memory cells is provided, and each of the dummy memory cells has a magneto-resistance element. Word lines are provided for the rows of the memory cells and the dummy memory cells, respectively, and bit lines are provided for the columns of the memory cells, respectively. A dummy bit line is provided for the column of dummy memory cells. A read circuit is connected with the cross point cell array and the dummy bit line.
摘要翻译： 在磁随机存取存储器中，存储单元的交叉点单元阵列以列和列的矩阵排列，并且每个存储单元都具有磁阻元件。 提供一列虚拟存储单元，并且每个虚拟存储单元都具有磁阻元件。 分别为存储器单元和虚拟存储单元的行提供字线，并且分别为存储单元的列提供位线。 为虚拟存储单元的列提供虚拟位线。 读取电路与交叉点单元阵列和虚拟位线连接。
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公开(公告)号：US20050024950A1
公开(公告)日：2005-02-03
申请号：US10934599
申请日：2004-09-03
IPC分类号： G11C11/14 , G11C7/06 , G11C11/15 , G11C11/16 , G11C16/04 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C13/004 , G11C7/06 , G11C11/16 , G11C11/1673 , G11C13/0061 , G11C2013/0047 , G11C2013/0054 , G11C2013/0057 , G11C2207/066
摘要： By first readout, the current input from a selected cell 13 is converted by a preamplifier 3 and a VCO 4 into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so as to be stored in a readout value register 6. A selected cell is then written to one of two storage states, and second readout is then carried out. The storage state of the selected cell is verified by comparing a count value of the counter for the second readout, a count value for the first readout as stored in a readout value register and a reference value stored in a reference value register 7 to one another. By the use of the VCO, the integrating capacitor for the current or reference pulse generating means, so far needed, may be eliminated to assure a small area, low power consumption and fast readout.
摘要翻译： 通过第一读出，来自所选单元13的当前输入由前置放大器3和VCO4转换为与当前值成反比的频率的脉冲，并且预设时间间隔内的脉冲数由计数器计数 以便存储在读出值寄存器6中。然后，将所选择的单元写入两个存储状态中的一个，然后执行第二读出。 通过将存储在读出值寄存器中的第一次读出的计数值和存储在参考值寄存器7中的参考值彼此进行比较来验证所选单元的存储状态 。 通过使用VCO，可以消除目前需要的电流或参考脉冲发生装置的积分电容器，以确保小面积，低功耗和快速读出。
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公开(公告)号：US08503222B2
公开(公告)日：2013-08-06
申请号：US13144480
申请日：2010-01-21
申请人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
发明人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , H01L43/08 , H03K19/1776 , H03K19/1778 , H03K19/18 , H03K19/20
摘要： A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.
摘要翻译： 非易失性逻辑电路包括输入部分，控制部分和输出部分。 输入部具有垂直的磁各向异性，并具有磁化状态可变的铁磁层。 控制部分包括铁磁层。 输出部分设置在输入部分和控制部分的附近，并且包括磁化状态可变的磁性隧道结元件。 基于磁化状态改变输入部的磁化状态。 输出部分的磁性隧道结元件的磁化状态基于控制部分的铁磁材料的磁化状态和输入部分的铁磁材料的磁化状态而改变。
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