公开(公告)号：US20170194458A1

公开(公告)日：2017-07-06

申请号：US14985406

申请日：2015-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/30 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/30 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/7856

Abstract: a semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. A lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin. The gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin. The second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.

公开(公告)号：US20170170322A1

公开(公告)日：2017-06-15

申请号：US14968910

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02631 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/76841 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin-type field effect transistor device including a substrate, at least one gate stack structure, spacers and source and drain regions is described. The gate stack structure is disposed on the substrate and the spacers are disposed on sidewalls of the gate stack structure. The source and drain regions are disposed in the substrate and located at opposite sides of the gate stack structures. A dielectric layer having contact openings is disposed over the substrate and covers the gate stack structures. Metal connectors are disposed within the contact openings and connected to the source and drain regions, and adhesion layers are sandwiched between the contact openings and the metal connectors located within the contact openings.

公开(公告)号：US20170141106A1

公开(公告)日：2017-05-18

申请号：US14941673

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US20170140992A1

公开(公告)日：2017-05-18

申请号：US14941679

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/76224 ,  H01L21/823418 ,  H01L27/0886 ,  H01L29/06 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/201 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: A FinFET including a substrate, a plurality of insulators disposed on the substrate, a gate stack and a strained material is provided. The substrate includes a plurality of semiconductor fins. The semiconductor fins include at least one active fin and a plurality of dummy fins disposed at two opposite sides of the active fin. The insulators are disposed on the substrate and the semiconductor fins are insulated by the insulators. The gate stack is disposed over portions of the semiconductor fins and over portions of the insulators. The strained material covers portions of the active fin that are revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.

公开(公告)号：US20170077302A1

公开(公告)日：2017-03-16

申请号：US14854772

申请日：2015-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Wen Cheng ,  Che-Cheng Chang ,  Mu-Tsang Lin ,  Bo-Feng Young ,  Cheng-Yen Yu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses.

Abstract translation: 本公开涉及一种半导体器件，其通过在与沟道区相邻的凹槽中形成介电材料来控制沟道区上的应变，以便提供对外延源极/漏极的应变诱导材料的体积和形状的控制 形成在凹部内的区域。 在一些实施例中，半导体器件具有布置在沟道区域的相对侧上的半导体本体的上表面内的凹槽中的外延源极/漏极区域。 栅极结构布置在沟道区域上方，并且电介质材料横向布置在外延源极/漏极区域和沟道区域之间。 电介质材料消耗一些体积的凹槽，从而减少在凹陷中形成的外延源极/漏极区域中的应变诱发材料的体积。

公开(公告)号：US09142672B2

公开(公告)日：2015-09-22

申请号：US14023012

申请日：2013-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Tung-Wen Cheng ,  Yi-Jen Chen ,  Yung-Jung Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L29/0603 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract translation: 提供了形成半导体器件结构的机构的实施例。 半导体器件结构包括形成在衬底上的衬底和栅叠层结构。 半导体器件结构还包括形成在栅极堆叠的侧壁上的栅极间隔物。 半导体器件结构包括形成在衬底中的掺杂区域。 半导体器件结构还包括与栅极间隔物相邻的应变源极和漏极（SSD）结构，并且掺杂区域与SSD结构相邻。 半导体器件结构包括SSD结构具有最靠近掺杂区的尖端，并且尖端基本上与栅极间隔物的内侧对准。

公开(公告)号：US12272595B2

公开(公告)日：2025-04-08

申请号：US17453872

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Che-Cheng Chang ,  Wen-Tung Chen ,  Yu-Cheng Liu ,  Horng-Huei Tseng

IPC: H01L21/768

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

公开(公告)号：US12057343B2

公开(公告)日：2024-08-06

申请号：US17349741

申请日：2021-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/764 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.

公开(公告)号：US11855217B2

公开(公告)日：2023-12-26

申请号：US17120814

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L23/535 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28008 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/4991 ,  H01L29/66795 ,  H01L29/785

Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

公开(公告)号：US11670635B2

公开(公告)日：2023-06-06

申请号：US17194835

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/66545

Abstract: A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.