公开(公告)号：US12027628B2

公开(公告)日：2024-07-02

申请号：US18303924

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/68 ,  H01L29/76

CPC classification number: H01L29/78645 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66969 ,  H01L29/685 ,  H01L29/7606 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US11837611B2

公开(公告)日：2023-12-05

申请号：US17000582

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen

IPC: H01L45/00 ,  H01L27/146 ,  H10N70/00

CPC classification number: H01L27/146 ,  H10N70/021 ,  H10N70/841

Abstract: Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.

公开(公告)号：US20230387235A1

公开(公告)日：2023-11-30

申请号：US18365995

申请日：2023-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/66545 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/0665

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US11823957B2

公开(公告)日：2023-11-21

申请号：US17141117

申请日：2021-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  I-Sheng Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823807 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31111 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78684 ,  H01L29/78696

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.

公开(公告)号：US20230343876A1

公开(公告)日：2023-10-26

申请号：US18332938

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H Diaz

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/0673 ,  H01L29/66742 ,  H01L27/092

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US11380803B2

公开(公告)日：2022-07-05

申请号：US16837051

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hou-Yu Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Yu-Lin Yang ,  I-Sheng Chen

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials. The first oxide layer is in direct contact with the isolation layer.

公开(公告)号：US11335604B2

公开(公告)日：2022-05-17

申请号：US16426552

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  I-Sheng Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Kai-Tai Chang

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L21/02

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed. The upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The first semiconductor layers are partially etched to reduce widths of the first semiconductor layers. An oxide layer is formed over the upper fin structure. A sacrificial gate structure is formed over the upper fin structure with the oxide layer. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed to form a gate space. The oxide layer is removed to expose the second semiconductor layers in the gate space. A gate structure is formed around the second semiconductor layers in the gate space.

公开(公告)号：US11227955B2

公开(公告)日：2022-01-18

申请号：US16578389

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

公开(公告)号：US11152481B2

公开(公告)日：2021-10-19

申请号：US16201523

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  I-Sheng Chen ,  Shao-Ming Yu ,  Tzu-Chiang Chen ,  Chih Chieh Yeh

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L29/10 ,  H01L27/06 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/40 ,  H01L29/165

Abstract: A method includes providing a substrate; forming a first structure over the substrate, the first structure including a first gate trench and a first channel exposed in the first gate trench; forming a second structure over the substrate, the second structure including a second gate trench and a second channel exposed in the second gate trench; depositing a gate dielectric layer covering surfaces of the first and second channels exposed in the respective first and second gate trenches; recessing the gate dielectric layer in the second gate trench to be lower than the gate dielectric layer in the first gate trench; and forming a gate electrode layer over the gate dielectric layer in the first and second gate trenches.

公开(公告)号：US20210313455A1

公开(公告)日：2021-10-07

申请号：US17352507

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/8234

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.