公开(公告)号：US20240194765A1

公开(公告)日：2024-06-13

申请号：US18425058

申请日：2024-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yoh-Rong Liu ,  Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Li-Chi Yu ,  Sen-Hong Syue

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

公开(公告)号：US12009407B2

公开(公告)日：2024-06-11

申请号：US18303841

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Yung-Cheng Lu ,  Che-Hao Chang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/0259 ,  H01L21/31116 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

公开(公告)号：US20230369428A1

公开(公告)日：2023-11-16

申请号：US17871403

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Sun ,  Wen-Kai Lin ,  Che-Hao Chang ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/66545

Abstract: Embodiments provide a two-tiered trench isolation structure under the epitaxial regions (e.g., epitaxial source/drain regions) of a nano-FET transistor device, and methods of forming the same. The first tier provides an isolation structure with a low k value. The second tier provides an isolation structure with a higher k value, with material greater density, and greater etch resistivity than the first tier isolation structure.

公开(公告)号：US20230268426A1

公开(公告)日：2023-08-24

申请号：US17676470

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6681 ,  H01L29/7851 ,  H01L21/02164 ,  H01L21/02167

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US20230261080A1

公开(公告)日：2023-08-17

申请号：US18297922

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Tzu-Chieh Su ,  Che-Hao Chang

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/66553

Abstract: A method includes forming a stack of layers comprising a plurality of semiconductor nanostructures, and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, depositing a first spacer layer extending into the lateral recesses, with the first spacer layer comprising a first dielectric material, depositing a second spacer layer on the first spacer layer, with the second spacer layer comprising a second dielectric material different from the first dielectric material, and trimming the first spacer layer and the second spacer layer to form inner spacers.

公开(公告)号：US20220376088A1

公开(公告)日：2022-11-24

申请号：US17815527

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

公开(公告)号：US11469229B2

公开(公告)日：2022-10-11

申请号：US17149950

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Szu-Ping Lee ,  Che-Hao Chang ,  Chun-Heng Chen ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration in a range of 5% to 30%; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer to a range of 1% to 5%; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

公开(公告)号：US11444177B2

公开(公告)日：2022-09-13

申请号：US16940226

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

公开(公告)号：US20210367063A1

公开(公告)日：2021-11-25

申请号：US17072719

申请日：2020-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

公开(公告)号：US20210242333A1

公开(公告)日：2021-08-05

申请号：US16941445

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02

Abstract: A method includes forming a fin extending from a substrate; forming an first isolation region along opposing sidewalls of the fin; forming a gate structure over the fin; forming an epitaxial source/drain region in the fin adjacent the gate structure; forming an etch stop layer over the epitaxial source/drain region and over the gate structure; forming a protection layer over the etch stop layer, the protection layer including silicon oxynitride; and forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.