公开(公告)号：US20240297076A1

公开(公告)日：2024-09-05

申请号：US18657243

申请日：2024-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chan Yen ,  Ching-Feng Fu ,  Chia-Ying Lee

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L2924/0002

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

公开(公告)号：US12009258B2

公开(公告)日：2024-06-11

申请号：US17227056

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chan Yen ,  Ching-Feng Fu ,  Chia-Ying Lee

IPC: H01L27/12 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L29/66 ,  H01L23/532 ,  H01L29/165

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

公开(公告)号：US20240145597A1

公开(公告)日：2024-05-02

申请号：US18402407

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu ,  Yun-Min Chang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/2236

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

公开(公告)号：US11935920B2

公开(公告)日：2024-03-19

申请号：US17874732

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L29/06 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L29/417 ,  H10B10/00

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H10B10/12

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

公开(公告)号：US20230352344A1

公开(公告)日：2023-11-02

申请号：US18344441

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Fu ,  Yu-Lien Huang ,  Tsai-Jung Ho ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L27/0924 ,  H01L29/66795

Abstract: A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.

公开(公告)号：US11728218B2

公开(公告)日：2023-08-15

申请号：US17232374

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Fu ,  Yu-Lien Huang ,  Tsai-Jung Ho ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L27/0924 ,  H01L29/66795

Abstract: A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.

公开(公告)号：US11545546B2

公开(公告)日：2023-01-03

申请号：US16917473

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L29/06 ,  H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L21/764 ,  H01L21/8238

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

公开(公告)号：US20220367198A1

公开(公告)日：2022-11-17

申请号：US17874694

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.

公开(公告)号：US20220336666A1

公开(公告)日：2022-10-20

申请号：US17852899

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu ,  Yun-Min Chang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/165 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

公开(公告)号：US20220336288A1

公开(公告)日：2022-10-20

申请号：US17232374

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Fu ,  Yu-Lien Huang ,  Tsai-Jung Ho ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L27/092 ,  H01L29/66

Abstract: A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.