公开(公告)号：US12009214B2

公开(公告)日：2024-06-11

申请号：US17814691

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Tzu-Hsuan Hsu ,  Feng-Chi Hung

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/28 ,  H01L21/762 ,  H01L23/544 ,  H01L27/146 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/2652 ,  H01L21/28114 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/14609 ,  H01L27/1464 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

公开(公告)号：US11996399B2

公开(公告)日：2024-05-28

申请号：US17651881

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/06515 ,  H01L2224/08052 ,  H01L2224/08146 ,  H01L2224/0913 ,  H01L2224/09515 ,  H01L2224/09517 ,  H01L2224/48463 ,  H01L2224/8122 ,  H01L2224/81359 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/056 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00012

Abstract: A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

公开(公告)号：US20230378000A1

公开(公告)日：2023-11-23

申请号：US18362707

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823878 ,  H01L27/0924 ,  H01L21/823821 ,  H01L21/76224 ,  H01L21/0228

Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

公开(公告)号：US11640986B2

公开(公告)日：2023-05-02

申请号：US17363645

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Tien-Shun Chang ,  Szu-Ying Chen ,  Chun-Feng Nieh ,  Sen-Hong Syue ,  Huicheng Chang

IPC: H01L29/76 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324

Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.

公开(公告)号：US20220384436A1

公开(公告)日：2022-12-01

申请号：US17818598

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

公开(公告)号：US20220359205A1

公开(公告)日：2022-11-10

申请号：US17814691

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Tzu-Hsuan Hsu ,  Feng-Chi Hung

IPC: H01L21/265 ,  H01L21/762 ,  H01L21/28 ,  H01L29/423 ,  H01L23/544 ,  H01L29/66 ,  H01L29/78 ,  H01L27/146

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

公开(公告)号：US11380782B2

公开(公告)日：2022-07-05

申请号：US16996665

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chien-Tai Chan ,  Liang-Yin Chen ,  Yee-Chia Yeo ,  Szu-Ying Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

公开(公告)号：US20210407847A1

公开(公告)日：2021-12-30

申请号：US16917159

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US20210328044A1

公开(公告)日：2021-10-21

申请号：US17363645

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Tien-Shun Chang ,  Szu-Ying Chen ,  Chun-Feng Nieh ,  Sen-Hong Syue ,  Huicheng Chang

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324

Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.

公开(公告)号：US20160247854A1

公开(公告)日：2016-08-25

申请号：US15144998

申请日：2016-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung ,  Chen-Jong Wang ,  Tzu-Hsuan Hsu

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14689

Abstract: A color filter array and micro-lens structure for imaging system and method of forming the color filter array and micro-lens structure. A micro-lens material is used to fill the space between the color filters to re-direct incident radiation, and form a convex micro-lens structure above a top surface of the color filters.

Abstract translation: 用于成像系统的滤色器阵列和微透镜结构以及形成滤色器阵列和微透镜结构的方法。 微透镜材料用于填充滤色器之间的空间以重新引导入射辐射，并且在滤色器的顶表面上方形成凸的微透镜结构。