公开(公告)号：US20240266341A1

公开(公告)日：2024-08-08

申请号：US18640167

申请日：2024-04-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Szu-Ying Chen ,  Dun-Nian Yaung

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18 ,  H01L27/146

CPC分类号： H01L25/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/06515 ,  H01L2224/08052 ,  H01L2224/08146 ,  H01L2224/0913 ,  H01L2224/09515 ,  H01L2224/09517 ,  H01L2224/48463 ,  H01L2224/8122 ,  H01L2224/81359 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437

摘要： A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

公开(公告)号：US20160338201A1

公开(公告)日：2016-11-17

申请号：US15225379

申请日：2016-08-01

申请人： MURATA MANUFACTURING CO., LTD.

发明人： Shinya KIYONO ,  Toshitaka HAYASHI ,  Sho FUJITA

IPC分类号： H05K1/18 ,  H05K1/09 ,  H01L23/00 ,  H05K3/32

CPC分类号： H05K1/181 ,  B22F1/0059 ,  B22F7/064 ,  B23K35/025 ,  B23K35/302 ,  H01B1/22 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13194 ,  H01L2224/13347 ,  H01L2224/13487 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29347 ,  H01L2224/2939 ,  H01L2224/29487 ,  H01L2224/81075 ,  H01L2224/81193 ,  H01L2224/81359 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8184 ,  H01L2224/83075 ,  H01L2224/8384 ,  H01L2924/12044 ,  H05K1/097 ,  H05K3/32 ,  H05K2201/0257 ,  H05K2201/10015 ,  H05K2203/1131 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0541 ,  H01L2924/01029 ,  H01L2924/01046

摘要： An electronic component module formed with the use of a copper particle paste which can ensure that even the inner part of a joint material is sintered, where copper particles are excellent in oxidation resistance, and a joint part is provided with high joint reliability; and a method for manufacturing the module.

摘要翻译： 一种电子部件模块，其特征在于，使用能够确保铜粒子的耐氧化性优异的连接材料的内部甚至烧结的铜粒子糊，并且接合部具有高的接头可靠性; 以及该模块的制造方法。

公开(公告)号：US11996399B2

公开(公告)日：2024-05-28

申请号：US17651881

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Szu-Ying Chen ,  Dun-Nian Yaung

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18 ,  H01L27/146

CPC分类号： H01L25/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/06515 ,  H01L2224/08052 ,  H01L2224/08146 ,  H01L2224/0913 ,  H01L2224/09515 ,  H01L2224/09517 ,  H01L2224/48463 ,  H01L2224/8122 ,  H01L2224/81359 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/056 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00012

摘要： A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

公开(公告)号：US20170294402A1

公开(公告)日：2017-10-12

申请号：US15632686

申请日：2017-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/32135 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/81085 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81232 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/06 ,  H01L2924/00

摘要： A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

公开(公告)号：US09129840B2

公开(公告)日：2015-09-08

申请号：US14470076

申请日：2014-08-27

申请人： FUJI ELECTRIC CO., LTD.

发明人： Norihiro Nashida

IPC分类号： H01L23/00 ,  H05K3/32 ,  H05K3/40 ,  H01L23/373 ,  H01L23/433 ,  H01L23/498 ,  H01L25/07 ,  H05K3/34

CPC分类号： H01L24/09 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/01 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/072 ,  H01L2224/0401 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11848 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/13369 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1623 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/81091 ,  H01L2224/81095 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81359 ,  H01L2224/81385 ,  H01L2224/8184 ,  H01L2224/92242 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/1304 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/35 ,  H01L2924/351 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4015 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/01 ,  H01L2224/80 ,  H01L2924/00012

摘要： When a conductive post is bonded to a bonding target member such as a semiconductor chip or an insulating substrate with conductive patterns by using metal nanoparticles, a strong bonding layer can be obtained by forming a bottom surface of the distal end of the conductive post in a concave shape.

摘要翻译： 当通过使用金属纳米颗粒将导电柱结合到诸如半导体芯片或具有导电图案的绝缘基板的接合目标构件时，可以通过将导电柱的远端的底表面形成在 凹形。

公开(公告)号：US09860989B2

公开(公告)日：2018-01-02

申请号：US15225379

申请日：2016-08-01

申请人： MURATA MANUFACTURING CO., LTD.

发明人： Shinya Kiyono ,  Toshitaka Hayashi ,  Sho Fujita

IPC分类号： H05K7/10 ,  H05K7/12 ,  H05K1/18 ,  H01B1/22 ,  H01L23/00 ,  H05K3/32 ,  B22F1/00 ,  B22F7/06 ,  H05K1/09 ,  H01L23/31 ,  B23K35/30 ,  B23K35/02

CPC分类号： H05K1/181 ,  B22F1/0059 ,  B22F7/064 ,  B23K35/025 ,  B23K35/302 ,  H01B1/22 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13194 ,  H01L2224/13347 ,  H01L2224/13487 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29347 ,  H01L2224/2939 ,  H01L2224/29487 ,  H01L2224/81075 ,  H01L2224/81193 ,  H01L2224/81359 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8184 ,  H01L2224/83075 ,  H01L2224/8384 ,  H01L2924/12044 ,  H05K1/097 ,  H05K3/32 ,  H05K2201/0257 ,  H05K2201/10015 ,  H05K2203/1131 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0541 ,  H01L2924/01029 ,  H01L2924/01046

摘要： An electronic component module formed with the use of a copper particle paste which can ensure that even the inner part of a joint material is sintered, where copper particles are excellent in oxidation resistance, and a joint part is provided with high joint reliability; and a method for manufacturing the module.

公开(公告)号：US09721855B2

公开(公告)日：2017-08-01

申请号：US14568356

申请日：2014-12-12

申请人： International Business Machines Corporation

发明人： Joseph Kuczynski ,  Phillip V. Mann ,  Kevin M. O'Connell ,  Arvind K. Sinha ,  Karl Stathakis

IPC分类号： B23K3/047 ,  B23K3/08 ,  H01L23/00 ,  H01L21/66 ,  B23K1/00 ,  B23K1/20 ,  B23K3/06

CPC分类号： H01L22/20 ,  B23K1/0016 ,  B23K1/20 ,  B23K3/047 ,  B23K3/0623 ,  B23K3/08 ,  H01L22/12 ,  H01L24/75 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/757 ,  H01L2224/81125 ,  H01L2224/81191 ,  H01L2224/81359 ,  H01L2224/818 ,  H01L2224/81908 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593

摘要： A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location.

公开(公告)号：US20170084562A1

公开(公告)日：2017-03-23

申请号：US15366543

申请日：2016-12-01

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Jyun-Ling Tsai ,  Chang-Lun Lu

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/13 ,  H01L21/4846 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1405 ,  H01L2224/14051 ,  H01L2224/145 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81193 ,  H01L2224/81359 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： A chip structure is provided, which includes: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on each of the conductive pads; a nickel layer formed on the first copper layer; a second copper layer formed on the nickel layer; and a tin layer formed on the second copper layer, thereby effectively reducing stresses.

公开(公告)号：US20160172326A1

公开(公告)日：2016-06-16

申请号：US14392281

申请日：2014-01-26

申请人： TSINGHUA UNIVERSITY

发明人： Jian CAI ,  Ziyu LIU ,  Qian WANG ,  Shuidi WANG ,  Yang HU ,  Yu CHEN

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/14051 ,  H01L2224/1705 ,  H01L2224/17107 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81201 ,  H01L2224/8122 ,  H01L2224/81345 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/8182 ,  H01L2224/81897 ,  H01L2224/81898 ,  H01L2224/81906 ,  H01L2224/94 ,  H01L2224/81

摘要： In view of the problems in all existing bonding methods, such as high temperature, high pressure, and high surface modification cost, etc., the present invention provides a bonding method and a bonding structure formed using the same, which can overcome such drawbacks and also achieve wafer-level bonding under a condition of normal temperature and low pressure. The bonding method comprises: generating bonding structures capable of being mutually mechanical interlocked, wherein, the frictional heat generated by the bonding structures capable of being mutually mechanical interlocked is higher than the bonding energy therebetween; and, utilizing the frictional heat generated by the bonding structures capable of being mutually mechanical interlocked to bond the bonding structures capable of being mutually mechanical interlocked.

摘要翻译： 鉴于所有现有的接合方法（如高温，高压，高表面改性成本等）的问题，本发明提供了一种能够克服这些缺陷的接合方法和使用其的接合结构， 也可以在正常温度和低压条件下实现晶圆级接合。 接合方法包括：产生能够相互机械互锁的接合结构，其中由能够互相机械互锁的接合结构产生的摩擦热高于其间的接合能; 并且利用由能够相互机械互锁的接合结构产生的摩擦热来结合能够相互机械互锁的接合结构。

公开(公告)号：US09117772B2

公开(公告)日：2015-08-25

申请号：US13527422

申请日：2012-06-19

申请人： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

发明人： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC分类号： H01L21/44 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/32135 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/81085 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81232 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/06 ,  H01L2924/00

摘要： A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

摘要翻译： 一种方法包括将第一包装部件的第一电连接器与第二包装部件的第二电连接器对准。 利用第一电​​连接器与第二电连接器对准，金属层被电镀在第一和第二电连接器上。 金属层将第一电连接器连接到第二电连接器。