公开(公告)号：US20240387411A1

公开(公告)日：2024-11-21

申请号：US18789106

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

公开(公告)号：US20240363464A1

公开(公告)日：2024-10-31

申请号：US18767895

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.

公开(公告)号：US20240071981A1

公开(公告)日：2024-02-29

申请号：US18499242

申请日：2023-11-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mao-Yen Chang ,  Chih-Wei Lin ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Chun-Cheng Lin ,  Tin-Hao Kuo ,  Yu-Chia Lai ,  Chih-Hsuan Tai

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/73 ,  H01L21/568 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/17179 ,  H01L2224/17517 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/92125

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

公开(公告)号：US11855232B2

公开(公告)日：2023-12-26

申请号：US17750419

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chih-Hao Chang ,  Chia-Hung Liu ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Po-Chun Lin

IPC: H01L31/0203 ,  H01L31/18 ,  H01L31/024 ,  H01L31/02

CPC classification number: H01L31/0203 ,  H01L31/02002 ,  H01L31/024 ,  H01L31/1892

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US20230352357A1

公开(公告)日：2023-11-02

申请号：US18351010

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Hsien Chiang ,  Yu-Chih Huang ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Chi-Hui Lai ,  Chiahung Liu ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L23/528 ,  H01L23/5226 ,  H01L21/565 ,  H01L21/76837 ,  H01L24/09 ,  H01L2224/02373

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

公开(公告)号：US20220375877A1

公开(公告)日：2022-11-24

申请号：US17365699

申请日：2021-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

公开(公告)号：US20210280511A1

公开(公告)日：2021-09-09

申请号：US17315365

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Tsung-Hsien Chiang ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Po-Chun Lin

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

公开(公告)号：US20200105638A1

公开(公告)日：2020-04-02

申请号：US16266276

申请日：2019-02-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Hsien Chiang ,  Yu-Chih Huang ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Chi-Hui Lai ,  Chiahung Liu ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.