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253 条记录 (耗时 0.031 秒)

    Inversion thickness reduction in high-k gate stacks formed by replacement gate processes
    41.
    发明授权
    Inversion thickness reduction in high-k gate stacks formed by replacement gate processes 有权
    通过替换栅极工艺形成的高k栅极叠层的反向厚度减小

    公开(公告)号：US09252229B2

    公开(公告)日：2016-02-02

    申请号：US13605267

    申请日：2012-09-06

    申请人： Takashi Ando ,  Vijay Narayanan

    发明人： Takashi Ando ,  Vijay Narayanan

    IPC分类号： H01L21/02 ,  H01L29/49 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/4966 ,  H01L21/28176 ,  H01L29/517 ,  H01L29/66606 ,  H01L29/7833

    摘要： A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (Å); and forming a metal gate material over the high-k dielectric layer.

    摘要翻译： 形成晶体管器件的方法包括在半导体衬底上形成对应于衬底中形成的掺杂源极和漏极区域之间的界面层; 在界面层上形成高介电常数（高k）层，高k层的介电常数大于约7.5; 在高k层上形成掺杂金属层; 进行热处理以使掺杂的金属层清除从界面层扩散的氧原子，使得界面层的最终厚度小于约5埃（）; 以及在高k电介质层上形成金属栅极材料。

    SCAVENGING METAL STACK FOR A HIGH-K GATE DIELECTRIC
    43.
    发明申请
    SCAVENGING METAL STACK FOR A HIGH-K GATE DIELECTRIC 有权
    用于高K栅介质的SCAVENGING金属叠层

    公开(公告)号：US20140001573A1

    公开(公告)日：2014-01-02

    申请号：US13547772

    申请日：2012-07-12

    申请人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

    发明人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

    IPC分类号： H01L29/78

    CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

    摘要翻译： 提供半导体结构。 该结构包括半导体材料的半导体衬底和具有介电常数大于硅的介电常数介电层的栅极电介质。 栅极电介质位于半导体衬底上。 栅电极邻接栅极电介质。 栅电极包括邻接栅电介质的下金属层，邻接下金属层的扫除金属层，与清扫金属层邻接的上金属层和邻接上金属层的硅层。 清除金属层响应于退火而在上金属层和硅层之间的界面处减少氧化层。

    LOW THRESHOLD VOLTAGE CMOS DEVICE
    44.
    发明申请
    LOW THRESHOLD VOLTAGE CMOS DEVICE 有权
    低电压电压CMOS器件

    公开(公告)号：US20130154019A1

    公开(公告)日：2013-06-20

    申请号：US13327870

    申请日：2011-12-16

    申请人： Takashi Ando ,  Changhwan Choi ,  Kisik Choi ,  Vijay Narayanan

    发明人： Takashi Ando ,  Changhwan Choi ,  Kisik Choi ,  Vijay Narayanan

    IPC分类号： H01L27/092 ,  H01L21/28

    CPC分类号： H01L21/823842 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28229 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.

    摘要翻译： 一种包括NMOS区和PMOS区的半导体器件; 所述NMOS区域具有包括第一高k栅极电介质，第一功函数设定金属和栅电极填充材料的栅极结构; 所述PMOS区域具有包括第二高k栅极电介质，第二功函数设定金属和栅电极填充材料的栅极结构; 其中所述第一栅极电介质不同于所述第二栅极电介质，并且所述第一功函数设定金属与所述第二功函数设定金属不同。 还公开了制造半导体器件的方法，其包括栅极最后工艺。

    Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices
    49.
    发明申请
    Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices 有权
    场效应晶体管器件的等效氧化物厚度

    公开(公告)号：US20110291198A1

    公开(公告)日：2011-12-01

    申请号：US12788454

    申请日：2010-05-27

    申请人： Takashi Ando ,  Changhwan Choi ,  Unoh Kwon ,  Vijay Narayanan

    发明人： Takashi Ando ,  Changhwan Choi ,  Unoh Kwon ,  Vijay Narayanan

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L21/823842 ,  H01L21/02164 ,  H01L21/02697 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/518

    摘要： A method for forming a field effect transistor device includes forming an oxide layer on a substrate, forming a dielectric layer on the oxide layer, forming a first TiN layer on the dielectric layer, forming a metallic layer on the first layer, forming a second TiN layer on the metallic layer, removing a portion of the first TiN layer, the metallic layer, and the second TiN layer to expose a portion of the dielectric layer, forming a layer of stoichiometric TiN on the exposed portion of the dielectric layer and the second TiN layer, heating the device, and forming a polysilicon layer on the device.

    摘要翻译： 一种形成场效应晶体管器件的方法包括在衬底上形成氧化物层，在氧化层上形成电介质层，在电介质层上形成第一TiN层，在第一层上形成金属层，形成第二TiN 去除一部分第一TiN层，金属层和第二TiN层以暴露介电层的一部分，在介电层的暴露部分上形成化学计量的TiN层，第二层 TiN层，加热器件，并在器件上形成多晶硅层。

    Structure and method to form input/output devices
    50.
    发明授权
    Structure and method to form input/output devices 有权
    结构和方法来形成输入/输出设备

    公开(公告)号：US08836037B2

    公开(公告)日：2014-09-16

    申请号：US13584156

    申请日：2012-08-13

    申请人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

    发明人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

    IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L27/088

    CPC分类号： H01L21/28185 ,  H01L21/02181 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

    摘要： A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

    摘要翻译： 有限数量的Hi-K材料的原子层沉积（ALD）循环，然后沉积层间电介质并施加另外的Hi-K材料并且可选但优选的退火提供了增加的Hi-K材料含量和增加的输入的击穿电压 与输入/输出（I / O）晶体管相比，与同一芯片或晶圆上形成的逻辑晶体管相比，同时提供I / O和逻辑晶体管的反型层的可扩展性，而不会明显地影响性能或偏置温度不稳定性（BTI）参数。