公开(公告)号：US20050012153A1

公开(公告)日：2005-01-20

申请号：US10887839

申请日：2004-07-12

申请人： Takashi Ipposhi

发明人： Takashi Ipposhi

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/522 ,  H01L27/01 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of an SOI substrate and a plurality of dummy gate electrodes are disposed covering the respective dummy active layers. The arrangement pattern of the dummy active layers and the arrangement pattern of the dummy gate electrodes nearly match, so that the dummy gate electrodes are aligned accurately on the dummy active layers.

摘要翻译： 晶体管区域是形成包括MOS晶体管的多个MOS晶体管的区域，虚设区域是位于螺旋电感器下面的区域。 在虚拟区域中，在SOI衬底的主表面上设置多个虚设有源层，并且设置覆盖各个虚拟有源层的多个虚拟栅极电极。 虚拟有源层的布置图案和虚拟栅极电极的布置图案几乎一致，使得虚拟栅电极在虚拟有源层上精确对准。

公开(公告)号：US06794717B2

公开(公告)日：2004-09-21

申请号：US09986004

申请日：2001-11-07

申请人： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2701

CPC分类号： H01L29/78615 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S257/904

摘要： It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “-” functions as a gate electrode of an original MOS transistor.

摘要翻译： 本发明的目的是提供具有SOI结构的半导体器件，其中可以以高稳定性固定由部分隔离区隔离的元件形成区域中的体区的电位。 在由部分氧化膜（31）隔离的元件形成区域中形成包括源极区（51），漏极区（61）和H栅电极（71）的MOS晶体管。 H栅电极（71）将从栅极宽度W方向形成的主体区域（13）与漏极区域（61）和源极区域（51）的源极区域（51）和漏极区域（61）相邻地隔离 ）通过“I”横向（图中的垂直方向），中心“ - ”用作原始MOS晶体管的栅电极。

公开(公告)号：US06627512B2

公开(公告)日：2003-09-30

申请号：US10090607

申请日：2002-03-06

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L2176

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L27/1203

摘要： In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

公开(公告)号：US06596615B2

公开(公告)日：2003-07-22

申请号：US09481385

申请日：2000-01-12

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

IPC分类号： H01L218238

CPC分类号： H01L29/66772 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/0638 ,  H01L29/78609

摘要： A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

公开(公告)号：US06495898B1

公开(公告)日：2002-12-17

申请号：US09639953

申请日：2000-08-17

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L2900

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L27/1203

摘要： In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

摘要翻译： 在组合隔离氧化膜（BT1）中，靠近栅电极（GT13）的部分通过SOI层（3）到达埋入氧化膜（2），而靠近另一栅电极（GT12）的部分具有截面形状 在其下部设置有井区。 组合隔离氧化膜（BT1）的边缘部分的形状在LOCOS隔离氧化膜中呈鸟喙的形式。 因此，限定栅极氧化膜（GO12，GO13）的边缘部分的部分的厚度局部增加。 这样提供了一种半导体器件及其制造方法，该半导体器件包括具有防止绝缘击穿而不增加其厚度的栅极氧化膜的MOS晶体管。

公开(公告)号：US06461935B2

公开(公告)日：2002-10-08

申请号：US09989152

申请日：2001-11-21

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor device having a trench-shaped isolator, adjacent to the semiconductor element region is formed having a width which is continuously decreased in the downward direction for relaxing the stress in the silicon layer. Embodiments include forming a patterned dielectric layer on an SOI substrate, forming sidewall spacers thereon, and etching the underlying silicon layer followed by oxidation or controlled etching to form the trench with downwardly decreasing side surfaces.

摘要翻译： 具有与半导体元件区域相邻的沟槽形隔离器的半导体器件形成为具有在向下方向上连续减小的宽度，以缓解硅层中的应力。 实施例包括在SOI衬底上形成图案化的电介质层，在其上形成侧壁间隔物，并蚀刻下面的硅层，接着进行氧化或受控蚀刻，以形成具有向下减少的侧表面的沟槽。

公开(公告)号：US06372599B1

公开(公告)日：2002-04-16

申请号：US09371027

申请日：1999-08-10

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The invention provides a semiconductor device having the trench-shaped isolator is provided with a portion which is adjacent to the semiconductor element region, of which the width is continuously decreased in the downward direction, and of which the surface is planarized near the semiconductor element region, for relaxing the stress in the silicon layer and being flat the surface of the trench-shaped insulator, and method of manufacturing the same.

公开(公告)号：US5841171A

公开(公告)日：1998-11-24

申请号：US746951

申请日：1996-11-18

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78654

摘要： In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

摘要翻译： 在形成SOI衬底的硅半导体层中的元件隔离区域时，在形成于SOI层上的氧化物膜上沉积预定厚度的氮化硅膜。 以活性区域的设计尺寸对氮化硅膜进行构图，并且在图案化的氮化硅膜的侧表面上形成氮化硅膜的侧壁。 使用氮化物膜作为氧化掩模进行第一LOCOS工艺。 去除由第一LOCOS工艺形成的LOCOS膜，以在侧壁下形成更窄的凹面。 然后，沉积另一个氮化硅膜，并除去形成凹部的部分。 然后，进行第二LOCOS工艺以形成LOCOS膜作为元件隔离区。 第二LOCOS工艺使用具有窄腔的氧化掩模，使得有源区域和元件隔离区域的边界处的应力减小，并且可以抑制鸟喙的生长。

公开(公告)号：US5214001A

公开(公告)日：1993-05-25

申请号：US640499

申请日：1991-01-14

申请人： Takashi Ipposhi ,  Kazuyuki Sugahara

发明人： Takashi Ipposhi ,  Kazuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/304 ,  H01L21/762

CPC分类号： H01L21/304 ,  H01L21/2026 ,  H01L21/76248

摘要： A manufacturing method of a semiconductor device having a planar single crystal semiconductor surface is disclosed. In the manufacturing method of a semiconductor device, an insulating film is formed on a semiconductor substrate, a noncrystal semiconductor film is formed on the insulating film, a stripe-like anti-reflection film is formed on the noncrystal semiconductor film, and laser beam is irradiated along the anti-reflection film. Because of the difference in temperature, a film with thicknesses different in a substrate region in which the anti-reflection film is formed and a region around it is formed. A film to be a machining allowance for polishing is formed on the single crystal semiconductor film, polishing is performed from the side of said film to be a machining allowance for polishing so that desired planar film thickness of the single crystal semiconductor film is implemented.

摘要翻译： 公开了具有平面单晶半导体表面的半导体器件的制造方法。 在半导体装置的制造方法中，在半导体基板上形成绝缘膜，在绝缘膜上形成非晶半导体膜，在非晶半导体膜上形成条状的防反射膜，激光束为 沿抗反射膜照射。 由于温度的差异，形成了在其中形成防反射膜的基板区域和其周围的区域具有不同厚度的膜。 在单晶半导体膜上形成作为研磨加工余量的膜，从所述膜的侧面进行研磨，作为研磨用的加工余量，从而实现单晶半导体膜的期望的平面膜厚。

公开(公告)号：US5061655A

公开(公告)日：1991-10-29

申请号：US653086

申请日：1991-02-11

申请人： Takashi Ipposhi ,  Kozuyuki Sugahara

发明人： Takashi Ipposhi ,  Kozuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/263 ,  H01L21/321 ,  H01L21/762

CPC分类号： H01L21/2026 ,  H01L21/321 ,  H01L21/76248 ,  Y10S117/904 ,  Y10S148/093 ,  Y10S148/154

摘要： A method of producing so-called SOI structures according to this invention includes the step of forming an opening for seeding after an insulating layer of predetermined thickness has been formed on a first monocrystal silicon layer. Further, a non-monocrystal layer, e.g., a polycrystal silicon layer is formed on the surface of the insulating layer. The surface of the polycrystal silicon layer is smoothed as by grinding. A reflection-preventive film is formed on the smoothed surface of the polycrystal silicon layer. The reflection-preventive film has a thin film region whose reflectance is substantially zero and a thick film region having a predetermined reflectance. During laser annealing, the reflection-preventive film produces a predetermined temperature distribution in the polycrystal silicon layer. The polycrystal silicon layer which has melted according to this temperature distribution recrystallizes from adjacent the seed portion and thereby forms a new monocrystal silicon layer over the entire surface. The smoothing process for the polycrystal silicon layer prevents any change in the reflectance of the reflection-preventive film and improves control on the temperature distribution in the polycrystal silicon layer.

摘要翻译： 根据本发明的制造所谓的SOI结构的方法包括在第一单晶硅层上形成预定厚度的绝缘层之后形成用于接种​​的开口的步骤。 此外，在绝缘层的表面上形成非单晶层，例如多晶硅层。 多晶硅层的表面通过研磨而平滑化。 在多晶硅层的平滑表面上形成防反射膜。 防反射膜具有反射率基本为零的薄膜区域和具有预定反射率的厚膜区域。 在激光退火期间，防反射膜在多晶硅层中产生预定的温度分布。 根据该温度分布熔融的多晶硅层从种子部分相邻再结晶，从而在整个表面上形成新的单晶硅层。 多晶硅层的平滑处理防止防反射膜的反射率的任何变化，并且改善对多晶硅层中的温度分布的控制。