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227 条记录 (耗时 0.034 秒)

    Heterojunction bipolar transistor and method for fabricating the same
    41.
    发明授权
    Heterojunction bipolar transistor and method for fabricating the same 失效
    异质结双极晶体管及其制造方法

    公开(公告)号：US06821870B2

    公开(公告)日：2004-11-23

    申请号：US10224468

    申请日：2002-08-21

    申请人： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

    发明人： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

    IPC分类号： H01L2122

    CPC分类号： H01L29/7378 ,  H01L29/161 ,  H01L29/66242

    摘要： A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

    摘要翻译： 通过依次堆叠Si集电极层，SiGeC基极层和Si发射极层来制造异质结双极晶体管。 通过使Si集电体层的SiGeC基底层的晶格应变量为1.0％以下，带隙可以窄于现有实际SiGe的带隙（Ge含量为10％左右），良好 结晶可以在热处理后保持。 结果，可以实现没有实际麻烦的窄带隙基。

    Method of manufacturing semiconductor device having source/drain regions included in a semiconductor layer formed over an isolation insulating film and a semiconductor device fabricated thereby
    42.
    发明授权
    Method of manufacturing semiconductor device having source/drain regions included in a semiconductor layer formed over an isolation insulating film and a semiconductor device fabricated thereby 失效
    制造包括在隔离绝缘膜上形成的半导体层中的源极/漏极区域的半导体器件的制造方法以及由此制造的半导体器件

    公开(公告)号：US06821856B2

    公开(公告)日：2004-11-23

    申请号：US10188108

    申请日：2002-07-03

    申请人： Takeshi Takagi

    发明人： Takeshi Takagi

    IPC分类号： H01L21336

    CPC分类号： H01L29/66651 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78639

    摘要： A semiconductor device comprises an Si substrate, an isolation insulating film formed on the Si substrate, an Si layer formed on the Si substrate, a gate oxide film formed on the Si layer, a gate electrode formed on the gate oxide film, a sidewall formed on the side face of the gate electrode, a gate silicide film formed on the gate electrode, source and drain regions formed at both the sides of the gate electrode and including a part of the Si layer, and a silicide film formed on the source and drain regions. Because the source and drain regions are formed on a layer-insulating film so as to be overlayed, it is possible to decrease the active region and cell area of a device. Thereby, a high-speed operation and high integration can be realized.

    摘要翻译： 半导体器件包括Si衬底，形成在Si衬底上的隔离绝缘膜，形成在Si衬底上的Si层，形成在Si层上的栅极氧化膜，形成在栅氧化膜上的栅电极，形成侧壁 在栅电极的侧面上，形成在栅电极上的栅极硅化物膜，形成在栅电极的两侧的源极和漏极区，并且包括一部分Si层，以及形成在源极上的硅化物膜 漏区。 因为源极和漏极区域形成在层间绝缘膜上以便被覆盖，所以可以减小器件的有源区域和单元面积。 由此，能够实现高速运转，高集成化。

    Semiconductor device
    43.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06642607B2

    公开(公告)日：2003-11-04

    申请号：US10061365

    申请日：2002-02-04

    申请人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

    发明人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

    IPC分类号： H01L2993

    CPC分类号： H01L29/93 ,  H01L27/0664 ,  H01L27/0808

    摘要： A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

    摘要翻译： 可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

    Method for driving variable resistance element, and nonvolatile memory device
    47.
    发明授权
    Method for driving variable resistance element, and nonvolatile memory device 有权
    用于驱动可变电阻元件的方法和非易失性存储器件

    公开(公告)号：US09142289B2

    公开(公告)日：2015-09-22

    申请号：US13883075

    申请日：2012-06-11

    申请人： Takeshi Takagi ,  Koji Katayama

    发明人： Takeshi Takagi ,  Koji Katayama

    IPC分类号： G11C11/21 ,  G11C13/00

    CPC分类号： G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/32

    摘要： A driving method for driving a variable resistance element and a nonvolatile memory device, which achieves stable storage operation. In a low resistance write process, a low resistance writing voltage pulse having the negative polarity is applied once to a variable resistance layer included in a variable resistance element while in a high resistance write process, a high resistance writing voltage pulse having the positive polarity is applied more than twice to the same variable resistance layer. Here, when a voltage value of one of the high resistance writing voltage pulses is VH1 and a voltage value of the other high resistance writing voltage pulse applied subsequently is VH2, VH1>VH2 is satisfied.

    摘要翻译： 用于驱动可变电阻元件和非易失性存储器件的驱动方法，其实现稳定的存储操作。 在低电阻写入处理中，具有负极性的低电阻写入电压脉冲在包括在可变电阻元件中的可变电阻层上施加一次，而在高电阻写入处理中，具有正极性的高电阻写入电压脉冲是 施加两倍以上的同一可变电阻层。 这里，当高电阻写入电压脉冲之一的电压值为VH1，随后施加的另一个高电阻写入电压脉冲的电压值为VH2时，满足VH1> VH2。

    Nonvolatile memory element comprising a resistance variable element and a diode
    48.
    发明授权
    Nonvolatile memory element comprising a resistance variable element and a diode 有权
    非易失性存储元件包括电阻可变元件和二极管

    公开(公告)号：US08796660B2

    公开(公告)日：2014-08-05

    申请号：US12375881

    申请日：2007-09-21

    申请人： Takeshi Takagi ,  Takumi Mikawa

    发明人： Takeshi Takagi ,  Takumi Mikawa

    IPC分类号： H01L29/02 ,  H01L47/00 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L31/0352 ,  H01L45/00 ,  H01L27/24 ,  H01L27/10 ,  H01L21/00 ,  G11C11/00

    CPC分类号： H01L45/04 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683

    摘要： A nonvolatile memory element (20) of the present invention comprises a resistance variable element (14) and a diode (18) which are formed on a substrate (10) such that the resistance variable element (14) has a resistance variable layer (11) sandwiched between a lower electrode (12) and an upper electrode (13), and the diode (18) which is connected in series with the resistance variable element (14) in the laminating direction and has an insulating layer or semiconductor layer (15) sandwiched between a first electrode (16) at the lower side and a second electrode (17) at the upper side. The resistance variable layer (11) is embedded in a first contact hole (21) formed on the lower electrode (12). A first area (22) where insulating layer or semiconductor layer (15) of the diode (18) is in contact with a first electrode (16) of the diode (18) is larger than at least one of a second area (23) where the resistance variable layer (11) is in contact with the upper electrode (13) and a third area (24) where the resistance variable layer (11) is in contact with the lower electrode (12).

    摘要翻译： 本发明的非易失性存储元件（20）包括形成在基板（10）上的电阻可变元件（14）和二极管（18），使得电阻可变元件（14）具有电阻变化层（11 ）和位于下电极（12）和上电极（13）之间的二极管（18），以及与电阻可变元件（14）在层叠方向上串联连接并具有绝缘层或半导体层（15）的二极管 ）夹在下侧的第一电极（16）和上侧的第二电极（17）之间。 电阻变化层（11）嵌入形成在下电极（12）上的第一接触孔（21）中。 二极管（18）的绝缘层或半导体层（15）与二极管（18）的第一电极（16）接触的第一区域（22）大于第二区域（23）中的至少一个， 其中电阻变化层（11）与上电极（13）接触，电阻变化层（11）与下电极（12）接触的第三区域（24）。

    Nonvolatile memory device and method for programming the same
    49.
    发明授权
    Nonvolatile memory device and method for programming the same 有权
    非易失性存储器件及其编程方法

    公开(公告)号：US08565004B2

    公开(公告)日：2013-10-22

    申请号：US13379463

    申请日：2011-06-28

    申请人： Mitsuteru Iijima ,  Takeshi Takagi ,  Koji Katayama

    发明人： Mitsuteru Iijima ,  Takeshi Takagi ,  Koji Katayama

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    摘要： A method for programming a nonvolatile memory device according to the present invention includes a step of detecting an excessively low resistance cell from among a plurality of memory cells (11) (S101); a step of changing the resistance value of a load resistor (121) to a second resistance value smaller than a first resistance value (S103); and a step of causing, by applying a voltage pulse to a series circuit including the excessively low resistance cell and the load resistor (121) having the second resistance value, a variable resistance element (105) included in the excessively low resistance cell to shift to a second high resistance state having a resistance value greater than that of the first low resistance state (S104).

    摘要翻译： 根据本发明的非易失性存储器件的编程方法包括从多个存储单元（11）中检测过低电阻单元的步骤（S101）; 将负载电阻器（121）的电阻值改变为小于第一电阻值的第二电阻值的步骤（S103）; 以及通过对包括过低电阻单元的串联电路和具有第二电阻值的负载电阻器（121）施加电压脉冲，使包含在过低电阻单元中的可变电阻元件（105）移位 到具有大于第一低电阻状态的电阻值的第二高电阻状态（S104）。