公开(公告)号：US10546780B2

公开(公告)日：2020-01-28

申请号：US15343557

申请日：2016-11-04

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Raja Selvaraj ,  Venugopal Gopinathan

IPC: H01L21/78 ,  H01L23/18 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02

Abstract: An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

公开(公告)号：US10236826B1

公开(公告)日：2019-03-19

申请号：US16000972

申请日：2018-06-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh Darwhekar ,  Apoorva Bhatia ,  Subhashish Mukherjee

IPC: H04B1/26 ,  H03B5/18 ,  H04B1/16 ,  H04B1/04 ,  H03D7/14

Abstract: A down converter, including first and second biasing circuits, mixer, and transformer coupled to receive amplifier output signal. The first and second biasing circuits each include a biasing transistor and a first and second node, respectively. Mixer includes first and second transistors coupled to first node and third and fourth transistors coupled to second node. The second and fourth transistors are coupled to a third node. The first and third transistors are coupled to a fourth node. Mixer also includes a first resistor coupled to the fourth node and a supply voltage node and a second resistor coupled to the third node and a supply voltage node. Transformer includes a primary winding coupled to receive the amplifier output signal and to a supply voltage and a secondary winding coupled to mixer and first biasing circuit at first node and coupled to mixer and second biasing circuit at second node.

公开(公告)号：US20180131545A1

公开(公告)日：2018-05-10

申请号：US15860988

申请日：2018-01-03

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Abhijit Anant Patki ,  Madhulatha Bonu ,  Kumar Anurag Shrivastava

IPC: H04L27/22 ,  H04L7/033 ,  H03K19/21 ,  H03L7/113 ,  H03L7/087 ,  H04L7/00

CPC classification number: H04L27/22 ,  H03D3/00 ,  H03K19/21 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H04L7/0087 ,  H04L7/0331 ,  H04L27/2271

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.

公开(公告)号：US20170353157A1

公开(公告)日：2017-12-07

申请号：US15173044

申请日：2016-06-03

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Kumar Anurag Shrivastava ,  Madhulatha Bonu

IPC: H03B5/04 ,  H03B5/06 ,  H03B5/12 ,  H03L7/00

CPC classification number: H03B5/06 ,  H03B5/04 ,  H03B5/1221 ,  H03B5/1234 ,  H03L3/00 ,  H03L7/00

Abstract: Methods and apparatus are disclosed to generate an oscillating output signal having a voltage swing greater than a voltage swing across nodes of active devices. An example oscillator includes a tank to generate an oscillating output signal in response receiving an edge of an enable signal; a feedback generator including a first gain stage forming a first feedback loop with the tank, the first feedback loop providing a first charge to maintain the oscillating output signal and a second gain stage forming a second feedback loop with the tank, the second feedback loop providing a second charge to maintain the oscillating output signal, the first and second charges combining with the oscillating output signal to generate a high voltage swing; and an attenuator connected between the tank and the feedback generator to isolate the tank from active components of the feedback generator.

公开(公告)号：US20170343589A1

公开(公告)日：2017-11-30

申请号：US15163380

申请日：2016-05-24

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Anoop Narayan Bhat

IPC: G01R19/04

CPC classification number: G01R19/04 ,  H03D1/2272 ,  H03D1/229

Abstract: A reduced-stage feedback-based envelope detector includes, for example, an input rectifier for rectifying a received modulated input signal and an amplifier for receiving the rectified modulated input signal at an input node. The amplifier compares the rectified modulated input signal with a reference signal, filters the rectified modulated input signal at the input node, and generates an envelope detection signal in response to the comparison and the filtering of the rectified modulated input signal. In an embodiment, the gain of the amplifier is independently determined from the bandwidth of the amplifier.

公开(公告)号：US09601995B1

公开(公告)日：2017-03-21

申请号：US15145775

申请日：2016-05-03

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Kumar Anurag Shrivastava

IPC: G01R19/00 ,  H02M3/07 ,  H03K3/0233 ,  H03K17/22

CPC classification number: H03K3/02337 ,  G01R19/04 ,  H03K9/02

Abstract: A low power radio frequency envelope detector includes a charging transistor for controlling the charge supplied to an output capacitor. A first input capacitor couples an input signal to a gate of the charging transistor. A second input capacitor couples a first polarity of the input signal to a first diode such that the first diode is operable to couple charge to the first input capacitor and to the gate of the charging transistor in response to a positive excursion of the first polarity of the input signal. A third input capacitor couples a second polarity of the input signal to a second diode coupled in series with the first diode. The first and second diodes are operable to couple charge to the first input capacitor and to the gate of the charging transistor in response to a positive excursion of the first polarity of the input signal.

公开(公告)号：US20240113722A1

公开(公告)日：2024-04-04

申请号：US18534861

申请日：2023-12-11

Applicant: Texas Instruments Incorporated

Inventor： Jayawardan Janardhanan ,  Yogesh Darwhekar ,  Subhashish Mukherjee

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.

公开(公告)号：US20230013907A1

公开(公告)日：2023-01-19

申请号：US17377698

申请日：2021-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Jayawardan Janardhanan ,  Yogesh Darwhekar

IPC: H03M1/10 ,  H03K5/135 ,  G04F10/00

Abstract: A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

公开(公告)号：US11515209B2

公开(公告)日：2022-11-29

申请号：US16773692

申请日：2020-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Raja Selvaraj ,  Venugopal Gopinathan

IPC: H01L21/78 ,  H01L23/58 ,  H01L23/66 ,  H01L23/18 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02

Abstract: An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

公开(公告)号：US11500336B1

公开(公告)日：2022-11-15

申请号：US17317628

申请日：2021-05-11

Applicant: Texas Instruments Incorporated

Inventor： Yogesh Darwhekar ,  Subhashish Mukherjee ,  Narala Raghavendra Reddy

IPC: H03M1/50 ,  G04F10/00 ,  G06F1/08 ,  H03M3/00 ,  G04G3/02

Abstract: An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.