公开(公告)号：US07728674B1

公开(公告)日：2010-06-01

申请号：US11437558

申请日：2006-05-19

Applicant: Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

Inventor： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC: H03L7/00

CPC classification number: H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

Abstract: Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

Abstract translation: 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

公开(公告)号：US20100073094A1

公开(公告)日：2010-03-25

申请号：US12234114

申请日：2008-09-19

Applicant: Tim Tri Hoang ,  Wilson Wong ,  Sergey Shumarayev

Inventor： Tim Tri Hoang ,  Wilson Wong ,  Sergey Shumarayev

IPC: H03L7/085

CPC classification number: H03L7/099 ,  H03L7/18

Abstract: A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

Abstract translation: 电路包括相位检测电路，时钟信号发生电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以产生控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值，以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值，以产生第二分频信号。 在不同的时间间隔期间，第一和第二分频信号作为反馈信号被路由到相位检测电路。

公开(公告)号：US07633349B2

公开(公告)日：2009-12-15

申请号：US11696575

申请日：2007-04-04

Applicant: Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

Inventor： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

IPC: H03L1/00

CPC classification number: H03D13/004

Abstract: A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

Abstract translation: 相位频率检测器将参考时钟信号与反馈时钟信号进行比较，以在一个或多个输出信号中产生脉冲。 一个或多个输出信号具有最小的脉冲宽度。 相位频率检测器具有温度检测电路。 相位频率检测器使用温度检测电路调节一个或多个输出信号的最小脉冲宽度，以补偿相位频率检测器的温度变化。

公开(公告)号：US20090122939A1

公开(公告)日：2009-05-14

申请号：US11329197

申请日：2006-01-09

Applicant: Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong ,  Rakesh H. Patel

Inventor： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong ,  Rakesh H. Patel

IPC: H04L7/00

CPC classification number: H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

Abstract: Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.

Abstract translation: 宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 可以在不关闭电路或PLD的情况下动态重新编程参数。 这允许CDR电路在各种标准和协议之间进行即时切换。

公开(公告)号：US07532029B1

公开(公告)日：2009-05-12

申请号：US11737079

申请日：2007-04-18

Applicant: Kazi Asaduzzaman ,  Leon Zheng ,  Sergey Shumarayev ,  Tim Tri Hoang

Inventor： Kazi Asaduzzaman ,  Leon Zheng ,  Sergey Shumarayev ,  Tim Tri Hoang

IPC: H03K19/173 ,  H03L7/00

CPC classification number: H03K19/1733 ,  H03K19/17752 ,  H03L7/081 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/0996 ,  H03L7/18

Abstract: Techniques are provided for dynamically reconfiguring programmable circuit blocks on integrated circuits during user mode. First configuration bits are loaded from first configuration scan registers into second configuration scan registers during configuration mode. The first configuration bits are used to configure programmable settings of a programmable circuit block. During user mode, second configuration bits are transmitted from a pin to the second configuration scan registers without transferring the second configuration bits through the first configuration scan registers. The second configuration bits are used to reconfigure the programmable settings of the programmable circuit block during the user mode. Also, phase shift circuitry can dynamically shift the phase of an output clock signal by selecting a different input clock signal. The phase shift circuitry has a delay circuit that allows the phase of a high frequency clock signal to be shifted without causing glitches in the clock signal.

Abstract translation: 提供技术用于在用户模式期间动态地重新配置集成电路上的可编程电路块。 在配置模式下，第一个配置位从第一个配置扫描寄存器加载到第二个配置扫描寄存器中。 第一个配置位用于配置可编程电路块的可编程设置。 在用户模式期间，第二配置位从引脚传输到第二配置扫描寄存器，而不通过第一配置扫描寄存器传输第二配置位。 第二个配置位用于在用户模式期间重新配置可编程电路块的可编程设置。 此外，相移电路可以通过选择不同的输入时钟信号来动态地移位输出时钟信号的相位。 相移电路具有允许高频时钟信号的相位被移位而不引起时钟信号的毛刺的延迟电路。

公开(公告)号：US20080258765A1

公开(公告)日：2008-10-23

申请号：US12214466

申请日：2008-06-18

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Richard G. Cliff

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Richard G. Cliff

IPC: H03K19/177 ,  H01L25/00

CPC classification number: H03K19/17744 ,  H03K19/17784

Abstract: High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.

Abstract translation: 可编程逻辑器件集成电路（“PLD”）上的高速串行接口或收发器电路包括允许PLD满足广泛可能的用户需求或应用的功能。 该范围包括高性能应用和PLD降低功耗很重要的应用。 在后一种情况下，可以使用各种特征中的任何一种或多种来帮助降低功耗。

公开(公告)号：US07414429B1

公开(公告)日：2008-08-19

申请号：US11486867

申请日：2006-07-14

Applicant: In Whan Kim ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Wilson Wong ,  Thungoc M. Tran

Inventor： In Whan Kim ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Wilson Wong ,  Thungoc M. Tran

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  H03K19/0175 ,  H01L25/00

CPC classification number: H03K19/17744

Abstract: The architecture of a programmable logic device (“PLD”) is modified in one or more of several respects to facilitate inclusion of high-speed serial interface (“HSSI”) circuitry in the PLD. For example, the HSSI circuitry is preferably located along one side of the device, taking the place of regular peripheral IO circuitry in that area. Certain portions of the core logic circuitry are modified to better interface with the HSSI circuitry.

Abstract translation: 可编程逻辑器件（“PLD”）的架构在几个方面中的一个或多个方面进行了修改，以便于在PLD中包含高速串行接口（“HSSI”）电路。 例如，HSSI电路优选地位于设备的一侧，代替该区域中的常规外设IO电路。 核心逻辑电路的某些部分被修改以更好地与HSSI电路接口。

公开(公告)号：US20080069276A1

公开(公告)日：2008-03-20

申请号：US11522284

申请日：2006-09-14

Applicant: Wilson Wong ,  Doris Po Ching Chan ,  Simardeep Maangat ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

Inventor： Wilson Wong ,  Doris Po Ching Chan ,  Simardeep Maangat ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC: H04B1/10

CPC classification number: H04L25/03885

Abstract: Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

Abstract translation: 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US08571059B1

公开(公告)日：2013-10-29

申请号：US13194536

申请日：2011-07-29

Applicant: Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

Inventor： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

IPC: H04J3/00

CPC classification number: G06F13/385

Abstract: Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.

Abstract translation: 公开了用于提供具有共享数据路径的串行接口的装置和方法。 该装置和方法共享或重新使用来自多个低速数据路径的组件，以便有效地提供更高速度的数据通路。 在一个实施例中，低速数据路径的物理编码子层电路也被较高速数据路径使用。 在另一个实施例中，低速数据路径的物理介质访问电路也被高速数据路径使用。 还公开了其它实施例，方面和特征。

公开(公告)号：US08208528B1

公开(公告)日：2012-06-26

申请号：US11955948

申请日：2007-12-13

Applicant: Tin H. Lai ,  Sergey Shumarayev ,  Tim Tri Hoang

Inventor： Tin H. Lai ,  Sergey Shumarayev ,  Tim Tri Hoang

IPC: H03H7/30

CPC classification number: H04B10/695

Abstract: Adaptation convergence in an adaptive dispersion compensation engine (ADCE) of a high-speed serial interface is detected by monitoring the output of the error amplifier of one or more adjustment loops of the ADCE. Adaptation convergence is considered to have been detected upon detection of a predetermined number of transitions in the error amplifier output, each of which occurs within a preselected interval following the previous transition. The detector may be implemented with a timer that times the preselected interval and a counter that counts transitions in the error amplifier output. The timer restarts each time a transition occurs, and the counter outputs a convergence signal when it reaches the predetermined number, but is reset each time the timer reaches the preselected interval. The serial interface may be part of a programmable integrated circuit device and in any case the preselected interval and the predetermined number may be programmable.

Abstract translation: 通过监视ADCE的一个或多个调节回路的误差放大器的输出来检测高速串行接口的自适应色散补偿引擎（ADCE）中的适应收敛。 认为在误差放大器输出中检测到预定数量的转换后已经检测到适应收敛，其中每一个都在先前转换之后的预选间隔内发生。 检测器可以用定时器实现，该定时器乘以预选间隔，而计数器可以对误差放大器输出中的转换进行计数。 定时器在每次转换发生时重新开始计时，当计数器达到预定数量时，计数器输出会聚信号，但每当定时器达到预先选定的时间间隔时，计数器都会被复位。 串行接口可以是可编程集成电路器件的一部分，并且在任何情况下，预选间隔和预定数量可以是可编程的。