公开(公告)号：US09621005B2

公开(公告)日：2017-04-11

申请号：US14436503

申请日：2013-02-15

Applicant: Toru Ishikawa ,  Yoshiro Imazawa

Inventor： Toru Ishikawa ,  Yoshiro Imazawa

IPC: H02K1/22 ,  H02K3/34 ,  H02K3/32 ,  H02K3/52

CPC classification number: H02K3/345 ,  H02K3/325 ,  H02K3/528

Abstract: There is provided a rotor of a rotating electrical machine including a pair of field core bodies that are provided so as to enclose the field coil via the insulation bobbin around which the field coil is wound, in which a claw-shaped magnetic pole extending from an outer circumferential section of the field core body in an axial direction is provided on the field core body. The insulation bobbin has a plurality of flange sections extending from the base section of the claw-shaped magnetic pole along an inner surface of the claw-shaped magnetic pole of the field core body, and a plurality of thin portions are formed in the root section of the flange section at intervals in a circumferential direction.

公开(公告)号：US09559381B2

公开(公告)日：2017-01-31

申请号：US13259042

申请日：2010-03-25

Applicant: Shinichi Komaba ,  Tomoaki Ozeki ,  Wataru Murata ,  Toru Ishikawa

Inventor： Shinichi Komaba ,  Tomoaki Ozeki ,  Wataru Murata ,  Toru Ishikawa

IPC: H01M10/0569 ,  H01M10/054 ,  H01M4/587

CPC classification number: H01M10/054 ,  H01M4/587 ,  H01M10/0569

Abstract: Disclosed is a sodium-ion secondary battery having excellent charge and discharge efficiencies as well as excellent charge and discharge characteristics, wherein charging and discharging can be repeated without causing problems such as deterioration in battery performance. Specifically disclosed is a sodium ion secondary battery which is provided with a positive electrode, a negative electrode having a negative electrode active material, and a nonaqueous electrolyte solution containing a nonaqueous solvent. The nonaqueous solvent is substantially composed of a saturated cyclic carbonate (excluding the use of ethylene carbonate by itself), or a mixed solvent of a saturated cyclic carbonate and a chain carbonate, and a hard carbon is used as the negative electrode active material. It is preferable that the nonaqueous solvent used for the sodium-ion secondary battery is substantially composed of propylene carbonate, a mixed solvent of ethylene carbonate and diethyl carbonate, or a mixed solvent of ethylene carbonate and propylene carbonate.

Abstract translation: 公开了具有优异的充放电效率以及优异的充放电特性的钠离子二次电池，其中可以重复充电和放电而不引起电池性能劣化等问题。 具体公开了一种钠离子二次电池，其具有正极，具有负极活性物质的负极和含有非水溶剂的非水电解液。 非水溶剂基本上由饱和环状碳酸酯（不包括使用碳酸亚乙酯本身）或饱和环状碳酸酯和链状碳酸酯的混合溶剂和硬碳作为负极活性物质组成。 用于钠离子二次电池的非水溶剂优选基本上由碳酸亚丙酯，碳酸亚乙酯和碳酸二乙酯的混合溶剂，碳酸亚乙酯和碳酸亚丙酯的混合溶剂组成。

公开(公告)号：US08958259B2

公开(公告)日：2015-02-17

申请号：US13444032

申请日：2012-04-11

Applicant: Kenichi Sakakibara ,  Toru Ishikawa

Inventor： Kenichi Sakakibara ,  Toru Ishikawa

IPC: G11C11/40 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40618

Abstract: Disclosed herein is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a plurality of memory cells, at least one data terminal, a data read/write circuit performing a data read operation to read out read-data from a selected one of the memory cells and supply the read-data to the data terminal and a data write operation to receive write-data from the data terminal and write the write-data into a selected one of the memory cells, and a refresh circuit performing a data refresh operation on selected one or ones of the memory cells of the memory cell array in response to an associated one of the refresh initiation signals taking the active level.

Abstract translation: 本文公开了一种包括多个存储器电路和刷新控制电路的装置，该刷新控制电路被配置为产生多个刷新启动信号，使得刷新启动信号中的一个获得有效电平。 每个存储器电路包括存储单元阵列，该存储单元阵列包括多个存储单元，至少一个数据端，数据读/写电路，执行数据读操作，以从所选存储单元中读出读数据并提供 读取数据到数据终端，以及数据写入操作，以从数据终端接收写入数据，并将写入数据写入所选择的一个存储器单元;以及刷新电路，对选择的一个或 所述存储器单元阵列的存储单元中的一个响应于所述刷新启动信号中的相关联的一个采用有效电平。

公开(公告)号：US08624401B2

公开(公告)日：2014-01-07

申请号：US13461627

申请日：2012-05-01

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/15311

Abstract: A device includes a semiconductor substrate, a first penetration electrode and a plurality of second penetration electrodes each penetrating the semiconductor substrate, a first terminal and a plurality of second terminals formed on a one side of the substrate, and a third terminal and a plurality of fourth terminals formed on an opposite side of the substrate. Each of the first and third terminals is vertically aligned with and electrically connected to first penetration electrode. Each of the second terminals is vertically aligned with an associated one of the second penetration electrodes and electrically connected to another one of the second penetration terminals that is not vertically aligned with the associated second terminal. Each of fourth terminals is vertically aligned with and electrically connected to an associated one of the second penetration electrodes.

Abstract translation: 一种器件包括半导体衬底，第一穿透电极和穿过半导体衬底的多个第二穿透电极，形成在衬底的一侧上的第一端子和多个第二端子，以及第三端子和多个 第四端子形成在基板的相对侧上。 第一和第三端子中的每一个与第一穿透电极垂直对准并电连接。 每个第二端子与第二穿透电极中的相关联的一个垂直对准，并且电连接到不与相关联的第二端子垂直对准的另一个第二穿透端子。 第四端子中的每一个与第二穿透电极中的相关联的一个垂直对准并电连接。

公开(公告)号：US08209560B2

公开(公告)日：2012-06-26

申请号：US12547863

申请日：2009-08-26

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: G06F1/12 ,  G06F13/42 ,  H04L7/00

CPC classification number: G06F1/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  H04L7/02 ,  H04L7/033

Abstract: To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and the data output circuit fetches data in response to multi-phase clock signals having different phases to be timing signals for fetching data, and adjusts a valid range for fetching data to be substantially uniform for each of the multi-phase clock signals. According to the present invention, the window width of data can be made uniform by individually adjusting the multi-phase clock signals that are input or output timing signals, and thus characteristics of the semiconductor device can be improved.

Abstract translation: 为了提供包括数据输入电路和数据输出电路的半导体器件，连接到多个数据输入/输出端子，其中数据输入电路和数据输出电路中的至少一个响应于多相时钟信号而取出数据 具有不同的相位作为用于取出数据的定时信号，并且调整用于将数据取出的有效范围对于每个多相时钟信号基本上是一致的。 根据本发明，可以通过单独调整作为输入或输出定时信号的多相时钟信号来使数据的窗口宽度均匀，从而可以提高半导体器件的特性。

公开(公告)号：US07990789B2

公开(公告)日：2011-08-02

申请号：US12320585

申请日：2009-01-29

Applicant: Shigeyuki Nakazawa ,  Toru Ishikawa

Inventor： Shigeyuki Nakazawa ,  Toru Ishikawa

IPC: G11C7/00

CPC classification number: G11C7/1048 ,  G11C29/1201 ,  G11C29/28 ,  G11C29/48 ,  G11C2029/1204 ,  G11C2029/2602

Abstract: A semiconductor memory device, in which a plurality of data output lines are commonly used by a plurality of banks, includes a plurality of gate circuits each of which are provided at each intermediate position of the plurality of the data output lines, and is controlled to be turned on during a normal operation mode and to be turned off at least when reading data during a parallel test mode, and a comparator circuit that inputs in parallel and compares a signal of each separated part of the each data output line separated by the plurality of the gate circuit being turned off.

Abstract translation: 其中多个数据输出线由多个组共同使用的半导体存储器件包括多个栅极电路，每个栅极电路设置在多个数据输出线的每个中间位置，并被控制为 在正常操作模式期间被接通并且至少在并行测试模式期间读取数据时被关闭，并且比较器电路并行输入并且比较由多个分离的每个数据输出线的每个分离部分的信号 的门电路被关闭。

公开(公告)号：US20110063017A1

公开(公告)日：2011-03-17

申请号：US12880730

申请日：2010-09-13

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H03K3/01

CPC classification number: H03K19/1732 ,  H03K19/018521 ,  H03K19/1733

Abstract: A semiconductor device includes a first circuit, a second circuit, and a first voltage dividing circuit. The first circuit is coupled to a first terminal. The first circuit is operable by a first voltage supplied from the first terminal. The second circuit is coupled through a first resistive element to the first terminal. The second circuit is operable by a second voltage supplied through the first resistive element from the first terminal. The second voltage is smaller in absolute value than the first voltage. The first voltage dividing circuit is coupled to a first node between the first resistive element and the second circuit. The first voltage dividing circuit has a conductive state and a non-conductive state. The first voltage dividing circuit is kept in the conductive state while applying the first voltage to the first terminal to allow the first circuit to operate by the first voltage.

Abstract translation: 半导体器件包括第一电路，第二电路和第一分压电路。 第一电路耦合到第一端子。 第一电路通过从第一端子提供的第一电压来操作。 第二电路通过第一电阻元件耦合到第一端子。 第二电路通过从第一端子通过第一电阻元件提供的第二电压来操作。 第二电压的绝对值比第一电压小。 第一分压电路耦合到第一电阻元件和第二电路之间的第一节点。 第一分压电路具有导通状态和非导通状态。 第一分压电路在将第一电压施加到第一端子的同时保持导通状态，以允许第一电路通过第一电压工作。

公开(公告)号：US20090206879A1

公开(公告)日：2009-08-20

申请号：US12379289

申请日：2009-02-18

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H03K19/094

CPC classification number: H04L25/0264 ,  H01L2224/48137 ,  H04L25/0278

Abstract: A signal transmission circuit includes first and second power source wirings, and a plurality of differential circuits connected in series between the first and second power source wirings. A signal transmission system includes a plurality of pairs of signal wirings, an output circuit supplying a differential signal to each of the pairs of signal wirings, and an input circuit receiving the differential signals via the pairs of signal wirings, wherein the output circuit includes first and second power source wirings, and a plurality of differential output circuits connected in series between the first and second power source wirings, and the input circuit includes a plurality of differential input circuits respectively corresponding to the differential output circuits.

Abstract translation: 信号传输电路包括第一和第二电源布线，以及串联连接在第一和第二电源布线之间的多个差分电路。 信号传输系统包括多对信号布线，输出电路向每对信号布线提供差分信号，以及输入电路经由信号配线对接收差分信号，其中输出电路包括第一 和第二电源布线，以及串联连接在第一和第二电源布线之间的多个差分输出电路，并且输入电路包括分别对应于差分输出电路的多个差分输入电路。

公开(公告)号：US20090196107A1

公开(公告)日：2009-08-06

申请号：US12360498

申请日：2009-01-27

Applicant: Tomohiro Ogasawara ,  Toru Ishikawa

Inventor： Tomohiro Ogasawara ,  Toru Ishikawa

IPC: G11C7/00

CPC classification number: G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096

Abstract: A semiconductor device selects one mask pattern among from a plurality of the mask patterns, which are stored in a mask resister circuit for mask controlling of a bit width (vertical axis), by a mask pattern selection signal, and controls input and output of data based on the selected mask pattern and a mask control signal of a bit string (horizontal axis), when inputting and outputting data having the consecutive bit string (horizontal axis) and a plurality of the bit widths (vertical axis). A read data converter circuit and a write data converter circuit select to mask or unmask each data signal during burst reading or writing, and masks the data signal. The masked data signal is not written in a memory cell by inactivating a write data buffer circuit during writing, and is not read out by inactivating a data driver circuit connecting with an external input and output terminal.

Abstract translation: 半导体器件通过掩模图案选择信号从存储在掩码寄存器电路中的多个掩模图案中选择一个掩模图案，以掩模控制位宽（垂直轴），并且控制数据的输入和输出 基于所选择的掩模图案和位串（水平轴）的掩码控制信号，当输入和输出具有连续位串（水平轴）和多个位宽（垂直轴）的数据时。 读数据转换器电路和写数据转换器电路在脉冲串读或写期间选择屏蔽或取消屏蔽每个数据信号，并对数据信号进行掩蔽。 掩蔽的数据信号在写入期间不使写数据缓冲电路失活而不写入存储单元，并且不通过使与外部输入和输出端连接的数据驱动电路失活来读出。

公开(公告)号：US20090190411A1

公开(公告)日：2009-07-30

申请号：US12320585

申请日：2009-01-29

Applicant: Shigeyuki Nakazawa ,  Toru Ishikawa

Inventor： Shigeyuki Nakazawa ,  Toru Ishikawa

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1048 ,  G11C29/1201 ,  G11C29/28 ,  G11C29/48 ,  G11C2029/1204 ,  G11C2029/2602

Abstract: A semiconductor memory device, in which a plurality of data output lines are commonly used by a plurality of banks, includes a plurality of gate circuits each of which are provided at each intermediate position of the plurality of the data output lines, and is controlled to be turned on during a normal operation mode and to be turned off at least when reading data during a parallel test mode, and a comparator circuit that inputs in parallel and compares a signal of each separated part of the each data output line separated by the plurality of the gate circuit being turned off.

Abstract translation: 其中多个数据输出线由多个组共同使用的半导体存储器件包括多个栅极电路，每个栅极电路设置在多个数据输出线的每个中间位置，并被控制为 在正常操作模式期间被接通并且至少在并行测试模式期间读取数据时被关闭，并且比较器电路并行输入并且比较由多个分离的每个数据输出线的每个分离部分的信号 的门电路被关闭。