公开(公告)号：US06872979B2

公开(公告)日：2005-03-29

申请号：US10357392

申请日：2003-02-04

申请人： Yoshiko Yoshida ,  Hideki Naruoka ,  Yasuhiro Kimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

发明人： Yoshiko Yoshida ,  Hideki Naruoka ,  Yasuhiro Kimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC分类号： H01L21/265 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/762 ,  H01L27/12 ,  H01L21/76

CPC分类号： H01L21/7624 ,  H01L21/3105 ,  H01L21/31155

摘要： A semiconductor substrate that prevents formation of particles from an edge part of the substrate. The substrate contains an on-substrate oxide film and an SOI layer stacked on the oxide film. A molten layer is formed on the edge part of the on-substrate oxide film and the SOI layer by mixing the SOI layer and the on-substrate oxide film to cover the edge part. An epitaxial layer may also be formed on the edge part of the on-substrate oxide film and the SOI layer to cover the edge part.

摘要翻译： 一种半导体衬底，其防止从衬底的边缘部分形成颗粒。 衬底包含衬底上氧化物膜和堆叠在氧化物膜上的SOI层。 通过混合SOI层和基板上氧化物膜以覆盖边缘部分，在衬底上氧化膜和SOI层的边缘部分上形成熔融层。 也可以在衬底上氧化膜的边缘部分和SOI层上形成外延层以覆盖边缘部分。

公开(公告)号：US06191450B1

公开(公告)日：2001-02-20

申请号：US08990285

申请日：1997-12-15

申请人： Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Yuichi Hirano

发明人： Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Yuichi Hirano

IPC分类号： H01L2900

CPC分类号： H01L21/765

摘要： An FS upper nitride film (15) is formed on the upper surface of an FS electrode (5). Therefore, the upper surface of the FS electrode (5) is not exposed even when an FS upper oxide film (41) is partially almost removed in the manufacturing process. Thus, a semiconductor device which prevents degradation in operation characteristics and reliability due to existence of an FS insulating layer can be provided.

摘要翻译： 在FS电极（5）的上表面上形成有FS上部氮化物膜（15）。 因此，即使在制造过程中FS上部氧化膜（41）被部分地几乎除去的情况下，也不会使FS电极（5）的上表面露出。 因此，可以提供防止由于FS绝缘层的存在而引起的操作特性和可靠性降低的半导体器件。

公开(公告)号：US06953979B1

公开(公告)日：2005-10-11

申请号：US09466934

申请日：1999-12-20

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US06818536B2

公开(公告)日：2004-11-16

申请号：US10423960

申请日：2003-04-28

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

IPC分类号： H01L2100

CPC分类号： H01L29/66772 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/0638 ,  H01L29/78609

摘要： A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

摘要翻译： 形成侧壁氧化物层和侧壁绝缘层以覆盖SOI层的边缘部分。 在SOI层的边缘部附近形成沟道阻挡区域。 在沟道阻挡区域上形成突出的绝缘层。 栅电极从SOI层上的区域延伸到突出的绝缘层和侧壁绝缘层。 以这种方式，可以抑制在SOI层的边缘部分处的寄生MOS晶体管的阈值电压Vth的降低。

公开(公告)号：US06646306B2

公开(公告)日：2003-11-11

申请号：US09985020

申请日：2001-11-01

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

IPC分类号： H01L2701

CPC分类号： H01L21/76286 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458

摘要： A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.

摘要翻译： 一种防止金属污染的半导体器件以及半导体器件的制造方法。 区域（NR）和区域（PR）由沟槽隔离氧化膜，选择性地设置在沟槽隔离氧化膜上的多晶硅膜，设置在多晶硅膜上的硅层和设置在侧面上的侧壁隔离物 多晶硅膜的表面。 多晶硅膜设置在对应于跨越两个阱区域的SOI层中的P型阱区域和N型阱区域的PN结部分JP的顶部的位置。

公开(公告)号：US06335267B1

公开(公告)日：2002-01-01

申请号：US09667498

申请日：2000-09-22

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Takashi Ipposhi ,  Shigenobu Maeda ,  Yuichi Hirano

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Takashi Ipposhi ,  Shigenobu Maeda ,  Yuichi Hirano

IPC分类号： H01L2120

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.

摘要翻译： 提供半导体衬底和制造半导体器件的方法。 氧化膜（13）通过氧化SOI衬底（10）的边缘部分和下主表面而形成。 通过使用暴露在SOI衬底（10）的边缘部分和下部主表面上的氧化膜（11）作为下面的氧化膜，以类似于LOCOS（硅的局部氧化物）氧化的方式进行该氧化步骤。 然后，氧化膜（13）的厚度大于SOI衬底（10）的边缘部分和下主表面上的氧化物膜（11）的厚度。 半导体衬底防止在其边缘处产生灰尘颗粒。

公开(公告)号：US6150696A

公开(公告)日：2000-11-21

申请号：US55903

申请日：1998-04-07

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Takashi Ipposhi ,  Shigenobu Maeda ,  Yuichi Hirano

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Takashi Ipposhi ,  Shigenobu Maeda ,  Yuichi Hirano

IPC分类号： H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.

公开(公告)号：US07482658B2

公开(公告)日：2009-01-27

申请号：US11677951

申请日：2007-02-22

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L21/00

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

摘要翻译： 在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。 电源线（21）形成在隔离绝缘膜（5）的上方。 在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。 换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面 ）。 利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

公开(公告)号：US07303950B2

公开(公告)日：2007-12-04

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US6124619A

公开(公告)日：2000-09-26

申请号：US877202

申请日：1997-06-17

申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L21/76 ,  H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L29/4232

摘要： In order to improve isolation between an FS (field shielding) electrode and a gate electrode (6), upper and lower major surfaces of a polysilicon layer (35) forming a principal part of an FS electrode (5) are covered with nitride films (SiN films) (34, 36) respectively. Therefore, it is possible to inhibit portions in the vicinity of edge portions of the polysilicon layer (35) from being oxidized by an oxidant following oxidation for forming a gate insulating film (14). Thus, the polysilicon layer (35) is inhibited from deformation following oxidation, whereby the distance between an FS electrode (5) and a gate electrode (6) is sufficiently ensured. Consequently, isolation between the FS electrode (5) and the gate electrode (6) is improved.

摘要翻译： 为了改善FS（场屏蔽）电极和栅电极（6）之间的隔离，形成FS电极（5）的主要部分的多晶硅层（35）的上主表面和下主表面被氮化物膜（ SiN膜）（34,36）。 因此，可以抑制多晶硅层（35）的边缘部分附近的部分被形成栅极绝缘膜（14）的氧化后的氧化剂氧化。 因此，抑制氧化后的多晶硅层（35）变形，从而充分确保了FS电极（5）与栅电极（6）之间的距离。 因此，提高了FS电极（5）与栅电极（6）之间的隔离。