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公开(公告)号：US20160148816A1
公开(公告)日：2016-05-26
申请号：US14549529
申请日：2014-11-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Rung-Yuan Lee , Yu-Ting Li , Jing-Yin Jhang , Chen-Yi Weng , Jia-Feng Fang , Yi-Wei Chen , Wei-Jen Wu , Po-Cheng Huang , Fu-Shou Tsai , Kun-Ju Li , Wen-Chin Lin , Chih-Chien Liu , Chih-Hsun Lin , Chun-Yuan Wu
IPC: H01L21/306 , H01L21/28
CPC classification number: H01L21/30625 , H01L21/28123 , H01L21/32115 , H01L21/3212
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成第一材料层; 在所述第一材料层上形成停止层; 在所述停止层上形成第二材料层; 并且进行平面化处理以去除第二材料层，停止层以及用于形成栅极层的第一材料层的一部分。
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公开(公告)号：US12232425B2
公开(公告)日：2025-02-18
申请号：US18515273
申请日：2023-11-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Si-Han Tsai , Dong-Ming Wu , Chen-Yi Weng , Ching-Hua Hsu , Ju-Chun Fan , Yi-Yu Lin , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang
Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
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公开(公告)号：US12201032B2
公开(公告)日：2025-01-14
申请号：US17223025
申请日：2021-04-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
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公开(公告)号：US20240365563A1
公开(公告)日：2024-10-31
申请号：US18762663
申请日：2024-07-03
Applicant: UNITED MICROELECTRONICS CORP
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.
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公开(公告)号：US11917923B2
公开(公告)日：2024-02-27
申请号：US17242322
申请日：2021-04-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ching-Hua Hsu , Si-Han Tsai , Shun-Yu Huang , Chen-Yi Weng , Ju-Chun Fan , Che-Wei Chang , Yi-Yu Lin , Po-Kai Hsu , Jing-Yin Jhang , Ya-Jyuan Hung
Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.
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Patent Agency Ranking
公开(公告)号：US20240065108A1
公开(公告)日：2024-02-22
申请号：US17944242
申请日：2022-09-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ching-Hua Hsu , Chen-Yi Weng , Jing-Yin Jhang , Po-Kai Hsu
CPC classification number: H01L43/12 , H01L43/08 , G11C11/161 , H01L43/02 , H01L27/222 , H01L43/10
Abstract: The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.
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公开(公告)号：US11849648B2
公开(公告)日：2023-12-19
申请号：US17341417
申请日：2021-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
CPC classification number: H10N50/80 , G11C5/06 , G11C11/16 , G11C11/161 , H01L29/82 , H10N50/01 , H10N50/10 , G11C2211/5615 , H10B61/00
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
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公开(公告)号：US20230329006A1
公开(公告)日：2023-10-12
申请号：US18207654
申请日：2023-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：US11716860B2
公开(公告)日：2023-08-01
申请号：US16882783
申请日：2020-05-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：US11616193B2
公开(公告)日：2023-03-28
申请号：US17338632
申请日：2021-06-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Chen-Yi Weng , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
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