公开(公告)号：US20140295650A1

公开(公告)日：2014-10-02

申请号：US13851113

申请日：2013-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jung Li ,  Chia-Jui Liang ,  Po-Chao Tsao ,  Ching-Ling Lin ,  En-Chiuan Liou

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

Abstract translation: 提供一种制造半导体器件的图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后在基板上顺序地形成目标层，硬掩模层和第一图案化掩模层。 通过使用第一图案化掩模层作为蚀刻掩模来执行第一蚀刻工艺，从而形成图案化的硬掩模层。 间隔物分别形成在图案化的硬掩模层的每个侧壁上。 然后，在基板上形成第二图案化掩模层。 执行第二蚀刻工艺以蚀刻第二区域中的图案化硬掩模层。 在间隔物曝光之后，将图案化的硬掩模层用作蚀刻掩模，并且去除曝光的目标层，直到相应的基板的曝光。

公开(公告)号：US20240202417A1

公开(公告)日：2024-06-20

申请号：US18179391

申请日：2023-03-07

Applicant: United Microelectronics Corp.

Inventor： Chia-Chen Sun ,  En-Chiuan Liou

IPC: G06F30/392 ,  G03F1/70

CPC classification number: G06F30/392 ,  G03F1/70

Abstract: A design method of a shuttle mask including the following steps is provided. A first integrated circuit (IC) design is provided in a first chip region, and a second IC design is provided in a second chip region. The first IC design includes first main patterns. The second IC design includes second main patterns. First dummy insertion patterns are added in the first chip region, and second dummy insertion patterns are added in the second chip region. The first main patterns and the first dummy insertion patterns are separated from each other. The first dummy insertion patterns are patterns formed by duplicating at least one of the first main patterns. The second main patterns and the second dummy insertion patterns are separated from each other. The second dummy insertion patterns are patterns formed by duplicating at least one of the second main patterns.

公开(公告)号：US20240012322A1

公开(公告)日：2024-01-11

申请号：US17878026

申请日：2022-07-31

Applicant: United Microelectronics Corp.

Inventor： Chia-Chen Sun ,  Song-Yi Lin ,  En-Chiuan Liou

IPC: G03F1/38 ,  G03F1/26

CPC classification number: G03F1/38 ,  G03F1/26

Abstract: A photomask structure including a layout pattern and at least one assist pattern is provided. The layout pattern includes corners. The assist pattern wraps at least one of the corners. There is a gap between the edge of the layout pattern and the assist pattern.

公开(公告)号：US10663853B2

公开(公告)日：2020-05-26

申请号：US15481479

申请日：2017-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F1/22 ,  G03F1/24

Abstract: An extreme ultraviolet (EUV) mask includes: a substrate having a first region and a second region; a reflective layer on the substrate; an absorbing layer on the reflective layer; and a first recess in the absorbing layer and in part of the reflective layer on the first region. Preferably, a bottom surface of the first recess exposes a top surface of the reflective layer.

公开(公告)号：US20200083020A1

公开(公告)日：2020-03-12

申请号：US16143419

申请日：2018-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01J37/302 ,  H01J37/317

Abstract: A method of pattern data preparation includes the following steps. A desired pattern to be formed on a surface of a layer is inputted. A first set of beam shots are determined, and a first calculated pattern on the surface is calculated from the first set of beam shots. The first calculated pattern is rotated, so that a boundary of the desired pattern corresponding to a non-smooth boundary of the first calculated pattern is parallel to a boundary constituted by beam shots. A second set of beam shots are determined to revise the non-smooth boundary of the first calculated pattern, thereby calculating a second calculated pattern being close to the desired pattern on the surface. The present invention also provides a method of forming a pattern in a layer.

公开(公告)号：US20200013783A1

公开(公告)日：2020-01-09

申请号：US16571202

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang ,  Sho-Shen Lee

IPC: H01L27/108 ,  G11C11/401

Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

公开(公告)号：US10529667B1

公开(公告)日：2020-01-07

申请号：US16049826

申请日：2018-07-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Zheng-Feng Chen ,  Sho-Shen Lee ,  En-Chiuan Liou ,  Hsiao-Lin Hsu ,  Yi-Ting Chen ,  Lu-Wei Kuo

IPC: H01L23/544 ,  H01L27/108 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/311

Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.

公开(公告)号：US10418290B2

公开(公告)日：2019-09-17

申请号：US15423544

申请日：2017-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Hon-Huei Liu ,  Chia-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/027 ,  H01L29/66

Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.

公开(公告)号：US10395999B1

公开(公告)日：2019-08-27

申请号：US15981053

申请日：2018-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hao Yang ,  En-Chiuan Liou ,  Hsiao-Lin Hsu ,  Tang-Chun Weng ,  Chia-Ching Lin ,  Yen-Pu Chen

IPC: H01L21/308 ,  H01L27/02 ,  H01L21/66 ,  H01L29/66

Abstract: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.

公开(公告)号：US10319856B2

公开(公告)日：2019-06-11

申请号：US15832755

申请日：2017-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/32 ,  H01L29/34 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.