公开(公告)号：US08928112B2

公开(公告)日：2015-01-06

申请号：US14337170

申请日：2014-07-21

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/00 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合，缓冲层的外侧壁和第一绝缘体的侧壁平整。

公开(公告)号：US20140332920A1

公开(公告)日：2014-11-13

申请号：US14337170

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. Apart of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 除了第一绝缘体和第二绝缘体之间的缓冲层界面之外，缓冲层的外侧壁和第一绝缘体的侧壁被平整。

公开(公告)号：US08765546B1

公开(公告)日：2014-07-01

申请号：US13925812

申请日：2013-06-24

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Chih-Sen Huang

IPC: H01L27/088

CPC classification number: H01L21/823431

Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a first gate structure on the fin-shaped structure; forming a first epitaxial layer in the fin-shaped structure adjacent to the first gate structure; forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer; forming an opening in the interlayer dielectric layer to expose the first epitaxial layer; forming a silicon cap on the first epitaxial layer; and forming a contact plug in the opening.

Abstract translation: 公开了一种用于制造鳍状场效应晶体管（FinFET）的方法。 该方法包括以下步骤：提供衬底; 在基板上形成翅片状结构; 在所述鳍状结构上形成第一栅极结构; 在与所述第一栅极结构相邻的所述鳍状结构中形成第一外延层; 在所述第一栅极结构和所述第一外延层上形成层间电介质层; 在所述层间电介质层中形成开口以暴露所述第一外延层; 在所述第一外延层上形成硅帽; 并在开口中形成接触塞。

公开(公告)号：US20250048648A1

公开(公告)日：2025-02-06

申请号：US18916746

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunneling junction (MTJ) on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes metal and the blocking layer includes a grid line pattern according to a top view.

公开(公告)号：US20240365679A1

公开(公告)日：2024-10-31

申请号：US18205570

申请日：2023-06-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Jia-Rong Wu ,  Rai-Min Huang ,  Po-Kai Hsu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01 ,  G11C11/161

Abstract: The invention provides a semiconductor layout pattern, which comprises a first metal layer, wherein the first metal layer comprises a plurality of first patterns and a plurality of fishbone line patterns arranged on the same layer, wherein each fishbone line pattern comprises a principal axis pattern extending along a first direction and a plurality of branches arranged along a second direction, and each first pattern is located between two adjacent branches and the principal axis pattern, and a second metal layer is located on the first metal layer. A plurality of magnetic tunnel junction (MTJ) elements located on the second metal layer, wherein each magnetic tunnel junction element is arranged in a rhombic shape.

公开(公告)号：US11800723B2

公开(公告)日：2023-10-24

申请号：US17019340

申请日：2020-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Hung-Yueh Chen ,  Rai-Min Huang ,  Jia-Rong Wu ,  Yu-Ping Wang

IPC: G11C11/16 ,  H10B61/00 ,  G11C5/06 ,  G11C5/02 ,  H10N50/80

CPC classification number: H10B61/20 ,  G11C5/025 ,  G11C5/06 ,  G11C11/161 ,  H10N50/80

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a first diffusion region and a second diffusion region extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, a first gate pattern and a second gate pattern extending along the second direction adjacent to one side of the first contact plug, and a third gate pattern and a fourth gate pattern extending along the second direction adjacent to another side of the first contact plug.

公开(公告)号：US20230247915A1

公开(公告)日：2023-08-03

申请号：US18132992

申请日：2023-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.

公开(公告)号：US20220392954A1

公开(公告)日：2022-12-08

申请号：US17888451

申请日：2022-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H01L43/02 ,  H01L43/12

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

公开(公告)号：US20180068951A1

公开(公告)日：2018-03-08

申请号：US15285471

申请日：2016-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.

公开(公告)号：US09754938B1

公开(公告)日：2017-09-05

申请号：US15187800

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Tong-Jyun Huang ,  Shih-Hung Tsai ,  Jia-Rong Wu ,  Tien-Chen Chan ,  Yu-Shu Lin ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.