公开(公告)号：US09985110B2

公开(公告)日：2018-05-29

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L29/267 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US09953982B1

公开(公告)日：2018-04-24

申请号：US15468084

申请日：2017-03-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L21/28 ,  H01L29/423 ,  H01L21/033

CPC classification number: H01L27/10823 ,  H01L21/28008 ,  H01L21/76224 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/4236

Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in a substrate; removing part of the STI to form a first trench; forming a cap layer in the first trench; forming a mask layer on the cap layer and the substrate; and removing part of the mask layer, part of the cap layer, and part of the STI to form a second trench.

公开(公告)号：US09640482B1

公开(公告)日：2017-05-02

申请号：US15097301

申请日：2016-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Min-Chuan Tsai ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Kuo-Chin Hung ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L29/45 ,  H01L23/522

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266

Abstract: The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.

公开(公告)号：US11799012B2

公开(公告)日：2023-10-24

申请号：US17012088

申请日：2020-09-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/423 ,  H10B12/00 ,  H01L21/285

CPC classification number: H01L29/4941 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/3213 ,  H01L29/42372 ,  H10B12/05 ,  H10B12/482 ,  H01L21/28518 ,  H01L21/28556 ,  H10B12/30

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US20220130839A1

公开(公告)日：2022-04-28

申请号：US17570345

申请日：2022-01-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Kai-Jiun Chang ,  Yi-An Huang ,  Tsun-Min Cheng

IPC: H01L27/108

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

公开(公告)号：US11239241B2

公开(公告)日：2022-02-01

申请号：US16583268

申请日：2019-09-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L27/108 ,  H01L21/768

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

公开(公告)号：US11088023B2

公开(公告)日：2021-08-10

申请号：US15927106

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Wei-Hsin Liu

IPC: H01L21/768 ,  H01L21/324 ,  H01L27/108 ,  H01L23/532 ,  H01L21/285

Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.

公开(公告)号：US20200258889A1

公开(公告)日：2020-08-13

申请号：US16858729

申请日：2020-04-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Chun-Chieh Chiu

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/3215 ,  H01L23/532

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

公开(公告)号：US10685964B2

公开(公告)日：2020-06-16

申请号：US16028364

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

公开(公告)号：US20200020698A1

公开(公告)日：2020-01-16

申请号：US16583268

申请日：2019-09-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L27/108 ,  H01L21/768

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.