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公开(公告)号：US09660042B1
公开(公告)日：2017-05-23
申请号：US15073633
申请日：2016-03-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Chih-Sen Huang
IPC: H01L29/78 , H01L21/768 , H01L29/45 , H01L29/08 , H01L21/265 , H01L21/3205 , H01L29/66 , H01L29/49 , H01L23/535
CPC classification number: H01L29/45 , H01L21/26506 , H01L21/32053 , H01L21/76802 , H01L21/76877 , H01L23/535 , H01L29/0847 , H01L29/41791 , H01L29/495 , H01L29/4966 , H01L29/66568 , H01L29/66795 , H01L29/78 , H01L29/785
Abstract: A semiconductor device and manufacturing method thereof are provided in the present invention. A second opening is formed corresponding to a gate structure after a step of forming a first opening corresponding to an epitaxial layer. After the step of forming the second opening, a pre-amorphization implantation process is performed to form an amorphous region in the epitaxial layer, and the influence of the process of forming the second opening on the amorphous region may be avoided. The semiconductor device formed by the manufacturing method of the present invention includes a contact structure and an alloy layer. The contact structure is disposed in the second opening for being electrically connected to a metal gate. The alloy layer is disposed on the metal gate and disposed between the metal gate and the contact structure. The alloy layer includes an alloy of the material of the metal gate.
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公开(公告)号：US09324610B2
公开(公告)日：2016-04-26
申请号：US14455939
申请日：2014-08-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Jia-Rong Wu , Tsung-Hung Chang , Ching-Ling Lin , Yi-Hui Lee , Chih-Sen Huang , Yi-Wei Chen , Chun-Hsien Lin
IPC: H01L21/02 , H01L21/768 , H01L29/78 , H01L23/535 , H01L29/66 , H01L23/485 , H01L23/532
CPC classification number: H01L21/76897 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L23/53266 , H01L23/535 , H01L29/665 , H01L29/785 , H01L2924/0002 , H01L2924/00
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个金属栅极的衬底，与所述至少一个金属栅极的两侧相邻的源极/漏极区域以及围绕所述至少一个金属栅极的层间电介质层 ; 在所述ILD层中形成多个接触孔以暴露所述源/漏区; 在所述接触孔中形成第一金属层; 执行第一热处理过程; 并执行第二热处理过程。
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公开(公告)号：US20160071800A1
公开(公告)日：2016-03-10
申请号：US14513230
申请日：2014-10-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Tsung-Hung Chang , Yi-Hui Lee , Chih-Sen Huang , Yi-Wei Chen , Chia Chang Hsu , Hsin-Fu Huang , Chun-Yuan Wu , Shih-Fang Tzou
IPC: H01L23/535 , H01L21/768
CPC classification number: H01L21/76879 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.
Abstract translation: 提供了包括电介质层，钛层，氮化钛层和金属的半导体结构。 电介质层设置在基板上，其中介电层具有通孔。 钛层覆盖通孔，其中钛层具有低于1500Mpa的拉伸应力。 氮化钛层共形地覆盖钛层。 金属填充通孔。 本发明还提供了一种用于形成所述半导体结构的半导体工艺。 半导体工艺包括以下步骤。 介电层形成在基板上，其中电介质具有通孔。 钛层保形地覆盖通孔，其中钛层具有低于500Mpa的压应力。 形成氮化钛层以保形地覆盖钛层。 金属填充通孔。
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公开(公告)号：US11957064B2
公开(公告)日：2024-04-09
申请号：US17967904
申请日：2022-10-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
CPC classification number: H10N50/80 , G11C5/06 , G11C11/16 , G11C11/161 , H01L29/82 , H10N50/01 , H10N50/10 , G11C2211/5615 , H10B61/00
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
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公开(公告)号：US20240081157A1
公开(公告)日：2024-03-07
申请号：US18502103
申请日：2023-11-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
CPC classification number: H10N50/80 , G11C5/06 , G11C11/16 , G11C11/161 , H01L29/82 , H10N50/01 , H10N50/10 , G11C2211/5615 , H10B61/00
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
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Patent Agency Ranking
公开(公告)号：US20210390993A1
公开(公告)日：2021-12-16
申请号：US17460348
申请日：2021-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Jing-Yin Jhang , Chien-Ting Lin
Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
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公开(公告)号：US20210226119A1
公开(公告)日：2021-07-22
申请号：US17223025
申请日：2021-04-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
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公开(公告)号：US11018184B2
公开(公告)日：2021-05-25
申请号：US16532492
申请日：2019-08-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Ying-Cheng Liu , Yi-Hui Lee , Chin-Yang Hsieh , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang
Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.
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公开(公告)号：US11005030B2
公开(公告)日：2021-05-11
申请号：US16297704
申请日：2019-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.
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公开(公告)号：US20200266335A1
公开(公告)日：2020-08-20
申请号：US16297704
申请日：2019-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , Chen-Yi Weng , Chin-Yang Hsieh , I-Ming Tseng , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.
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