公开(公告)号：US20120037962A1

公开(公告)日：2012-02-16

申请号：US12854352

申请日：2010-08-11

申请人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/7682 ,  H01L21/31144 ,  H01L23/4821 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5329 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

摘要翻译： 公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。 具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。 定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。 还公开了使用自组装方法形成这种半导体结构的方法的实施例。

公开(公告)号：US08629008B2

公开(公告)日：2014-01-14

申请号：US13348018

申请日：2012-01-11

申请人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/02

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。

公开(公告)号：US20130175622A1

公开(公告)日：2013-07-11

申请号：US13348018

申请日：2012-01-11

申请人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。

公开(公告)号：US08390079B2

公开(公告)日：2013-03-05

申请号：US12914132

申请日：2010-10-28

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

IPC分类号： H01L27/088

CPC分类号： H01L29/4991 ,  H01L21/823468 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.

摘要翻译： 一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。

公开(公告)号：US20120199886A1

公开(公告)日：2012-08-09

申请号：US13020107

申请日：2011-02-03

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/7833

摘要： A semiconductor chip, including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a source and a drain in the substrate adjacent to the gate; a tapered contact contacting a portion of one of the source or the drain; and a sealed air gap between the sidewall and the contact.

摘要翻译： 一种半导体芯片，包括基板; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 邻近栅极的衬底中的源极和漏极; 与所述源极或所述漏极中的一个的一部分接触的锥形接触; 以及侧壁和接触件之间的密封气隙。

公开(公告)号：US08030202B1

公开(公告)日：2011-10-04

申请号：US12964831

申请日：2010-12-10

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An exemplary method lines the sidewalls of a first opening with a sacrificial material and then fills the first opening with a metallic conductor in a manner such that the metallic conductor contacts the substrate. Next, the method selectively removes the sacrificial material, to create at least one “second” opening along the metallic conductor within the first opening. The method selectively removes portions of the first insulator layer through the second opening to leave at least one air gap between the metallic conductor and the first insulator layer in the lower region of the second opening.

摘要翻译： 示例性方法用牺牲材料排列第一开口的侧壁，然后以金属导体接触基板的方式用金属导体填充第一开口。 接下来，该方法选择性地去除牺牲材料，以在第一开口内沿着金属导体产生至少一个“第二”开口。 所述方法通过所述第二开口选择性地去除所述第一绝缘体层的部分，以在所述第二开口的下部区域中留下所述金属导体和所述第一绝缘体层之间的至少一个气隙。

公开(公告)号：US08232618B2

公开(公告)日：2012-07-31

申请号：US12854352

申请日：2010-08-11

申请人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

发明人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

IPC分类号： H01L29/00

CPC分类号： H01L21/7682 ,  H01L21/31144 ,  H01L23/4821 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5329 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

摘要翻译： 公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。 具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。 定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。 还公开了使用自组装方法形成这种半导体结构的方法的实施例。

公开(公告)号：US20120104512A1

公开(公告)日：2012-05-03

申请号：US12914132

申请日：2010-10-28

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/823468 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.

摘要翻译： 一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。

公开(公告)号：US08124525B1

公开(公告)日：2012-02-28

申请号：US12913143

申请日：2010-10-27

申请人： Charles W. Koburger, III ,  David V. Horak ,  Shom Pomoth ,  Chih-Chao Yang ,  Su Chen Fan ,  Sivananda K. Kanakasabapathy

发明人： Charles W. Koburger, III ,  David V. Horak ,  Shom Pomoth ,  Chih-Chao Yang ,  Su Chen Fan ,  Sivananda K. Kanakasabapathy

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide a method of forming local interconnect for semiconductor devices. The method includes depositing a blanket layer of conductive material over one or more semiconductor devices; creating a pattern of local interconnect covering a portion of the blanket layer of conductive material; removing rest of the blanket layer of conductive material that is not covered by the pattern of local interconnect; forming the local interconnect by the portion of the blanket layer of conductive material to connect the one or more semiconductor devices.

摘要翻译： 本发明的实施例提供一种形成用于半导体器件的局部互连的方法。 该方法包括在一个或多个半导体器件上沉积导电材料的覆盖层; 产生覆盖导电材料的覆盖层的一部分的局部互连图案; 去除未被局部互连图案覆盖的导电材料的覆盖层的其余部分; 通过导电材料的覆盖层的部分形成局部互连以连接一个或多个半导体器件。

公开(公告)号：US20130320411A1

公开(公告)日：2013-12-05

申请号：US13488581

申请日：2012-06-05

申请人： Su-Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Su-Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545

摘要： A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.