公开(公告)号：US08788862B1

公开(公告)日：2014-07-22

申请号：US13175745

申请日：2011-07-01

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： G06F1/32

CPC分类号： G06F1/3278 ,  Y02D10/157 ,  Y02D50/20

摘要： A method and system for efficiently transitioning a communication circuit from a low-power state are disclosed. A first device and second device in a low-power state may be transitioned to an active state to enable the transmission of data over a communication link, where energy consumption of one or more components of the first and/or second devices may be reduced in the low-power state. The transition may be initiated by the first device responsive to a signal and/or an expiration of a timer. Responsive thereto, a scrambler of the first device may be temporarily bypassed to accelerate achieving block lock at the second device, thereby enabling the system to more quickly transition from the low-power state to the active state.

摘要翻译： 公开了一种将通信电路从低功率状态有效地转变的方法和系统。 处于低功率状态的第一设备和第二设备可以被转换到活动状态，以便能够通过通信链路传输数据，其中可以减少第一和/或第二设备中的一个或多个组件的能量消耗 低功耗状态。 第一设备可以响应于信号和/或定时器的期满而启动转换。 响应于此，第一设备的加扰器可能被暂时旁路以加速实现第二设备处的块锁定，从而使得系统能够更快地从低功率状态转换到活动状态。

公开(公告)号：US08732375B1

公开(公告)日：2014-05-20

申请号：US12752641

申请日：2010-04-01

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： G06F13/14

CPC分类号： G06F13/385

摘要： Structures and methods are disclosed relating to a multi-protocol transceiver including lane-based Physical Coding Sublayer (“PCS”) circuitry that is configurable to adapt to one of a plurality of communication protocols. Particular embodiments of the present invention include lane based configurable data paths through PCS transmit and receive circuitry.

摘要翻译： 公开了涉及包括基于通道的物理编码子层（“PCS”）电路的多协议收发器的结构和方法，该电路可配置为适应多个通信协议之一。 本发明的特定实施例包括通过PCS发送和接收电路的基于通道的可配置数据路径。

公开(公告)号：US20120307878A1

公开(公告)日：2012-12-06

申请号：US12860482

申请日：2010-08-20

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： H04B3/46 ,  H04L27/00

CPC分类号： H04L5/1446 ,  H04L1/0002 ,  H04L1/0025

摘要： An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.

摘要翻译： 用于本地设备的接口包括可编程地配置为至少三个数据速率的发射机部分，可编程地配置为至少三个数据速率的接收机部分，以及可操作地连接到发射机部分和接收机部分的自动速度协商模块 配置发射机部分和接收机部分，以与作为这些至少三个数据速率中最好的可用数据速率的单个数据速率与远程设备进行通信。 可以通过调整发射机数据路径宽度和接收机数据路径宽度，调整所述发射机数据路径和所述接收机数据路径的频率以及过采样来调整日期速率。 可以使能或禁用字节序列化或反序列化，以根据数据速率改变数据的宽度，以传输到/从本地设备的其余部分。

公开(公告)号：US07684477B1

公开(公告)日：2010-03-23

申请号：US11490406

申请日：2006-07-19

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： H04B3/46

CPC分类号： H04L1/0002

摘要： A serial interface for a programmable logic device includes receiver and transmitter portions, and an automatic speed negotiation module to adjust the data rates of both portions. The speed adjustment may be accomplished by adjusting the widths of the data paths in both portions. The speed adjustment occurs on receipt of a control signal generated elsewhere on the programmable logic device, or generated by the module. One reason for generating the control signal is the detection of data errors in the received data, or the detection of a delimiter pattern in the received data signifying that a remote device is about to change its data rate.Similarly, before changing its data rate, the module may insert a delimiter in the data in the transmitter portion. After receipt or transmission of a delimiter pattern, the module may wait for a predetermined delay period to elapse before changing the data rate.

摘要翻译： 用于可编程逻辑器件的串行接口包括接收器和发送器部分，以及用于调整两部分的数据速率的自动速度协商模块。 速度调整可以通过调整两部分中数据路径的宽度来实现。 速度调整发生在接收到可编程逻辑器件其他地方生成的或由模块生成的控制信号。 产生控制信号的一个原因是检测接收到的数据中的数据错误，或者检测到接收到的数据中的定界符模式，这意味着远程设备即将改变其数据速率。 类似地，在改变其数据速率之前，模块可以在发射机部分的数据中插入定界符。 在接收或发送分隔符模式之后，模块可以在改变数据速率之前等待预定的延迟时间段。

公开(公告)号：US20100058099A1

公开(公告)日：2010-03-04

申请号：US12576507

申请日：2009-10-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： G06F1/04 ,  G06F1/12

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US07138837B2

公开(公告)日：2006-11-21

申请号：US10349541

申请日：2003-01-21

申请人： Ramanand Venkata ,  Chong H. Lee ,  Henry Lui

发明人： Ramanand Venkata ,  Chong H. Lee ,  Henry Lui

IPC分类号： H03L7/00

CPC分类号： H03L7/089 ,  H03L2207/50 ,  H04L7/0337

摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal.

摘要翻译： 锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。

公开(公告)号：US07064685B1

公开(公告)日：2006-06-20

申请号：US10969448

申请日：2004-10-20

申请人： Ning Xue ,  Chong H. Lee

发明人： Ning Xue ,  Chong H. Lee

IPC分类号： H03M7/00

CPC分类号： H04L25/4908

摘要： A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).

摘要翻译： 用于填充协议接口的数据转换器或“变速箱”通过处理较窄的中间数据流来减少数量的组件，同时将其中间输入和输出的时钟速度乘以使其处理更多的数据 时钟周期。 数据流可以缩小为原始宽度（原始宽度除外）的任何整数因子。

公开(公告)号：US06963223B2

公开(公告)日：2005-11-08

申请号：US10835081

申请日：2004-04-28

申请人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

IPC分类号： H03K19/177 ,  H04Q11/04

CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H04J3/1617 ,  H04J2203/0082 ,  H04J2203/0094

摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

公开(公告)号：US06854044B1

公开(公告)日：2005-02-08

申请号：US10317262

申请日：2002-12-10

申请人： Ramanand Venkata ,  Chong H. Lee

发明人： Ramanand Venkata ,  Chong H. Lee

IPC分类号： G06F12/00 ,  G06F13/40 ,  H04J3/06

CPC分类号： G06F13/4018 ,  H04J3/0608

摘要： Circuitry for locating the boundaries between bytes in a data stream is only selectively enabled to find a possible new byte alignment by a control signal. After the byte alignment circuitry has found a byte alignment, it outputs byte-aligned data and a first status signal indicating the presence of such data. If the byte alignment circuitry subsequently detects information that suggests a possible need for a new or changed byte alignment, it outputs a second status signal to that effect. However, the byte alignment circuitry does not actually attempt to change its byte alignment until enabled to do so by the control signal. Programmable logic circuitry or other utilization circuitry is typically provided to receive the outputs of the byte alignment circuitry and to selectively provide the control signal.

摘要翻译： 用于定位数据流中的字节之间的边界的电路仅被选择性地用于通过控制信号找到可能的新字节对齐。 在字节对齐电路找到一个字节对齐之后，它输出字节对齐的数据和指示这种数据的存在的第一状态信号。 如果字节对齐电路随后检测出可能需要新的或改变的字节对齐的信息，则输出第二状态信号。 然而，字节对齐电路实际上并不会尝试改变其字节对齐，直到通过控制信号使其能够这样做。 通常提供可编程逻辑电路或其他利用电路以接收字节对准电路的输出并选择性地提供控制信号。

公开(公告)号：US06771105B2

公开(公告)日：2004-08-03

申请号：US10099707

申请日：2002-03-13

申请人： Stjepan William Andrasic ,  Rakesh H. Patel ,  Chong H. Lee

发明人： Stjepan William Andrasic ,  Rakesh H. Patel ,  Chong H. Lee

IPC分类号： H03H1126

CPC分类号： H03K5/133 ,  H03K3/0322 ,  H03K3/354 ,  H03L7/0995 ,  H03L7/10

摘要： A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

摘要翻译： 延迟单元具有可并行操作的并联负载电阻晶体管的可选数量，以及可并联连接的类似可选数量的偏置电流晶体管。 延迟单元优选在构造和操作上是不同的。 压控振荡器（“VCO”）包括以闭环系列连接的多个这样的延迟单元。 锁相环（“PLL”）电路包括由相位/频率检测器电路控制的这种VCO。 由于能够控制在每个延迟单元中有效或无效的负载电阻晶体管和偏置电流晶体管的数量，PLL可以具有非常宽的工作频率范围。 这种激活/去激活可以是可编程的或以其他方式控制的。