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公开(公告)号：US5757175A
公开(公告)日：1998-05-26
申请号：US782036
申请日：1997-01-13
IPC分类号： G05F3/26 , G05F3/24 , G11C11/407 , H03F3/343 , G05F3/16
CPC分类号： G05F3/242
摘要： A current source is provided between a first p channel MOS transistor and a ground node, and a current/voltage converting element is provided isolatedly from the current source between the ground node and a second p channel MOS transistor having a conductance coefficient sufficiently larger than that of the first MOS transistor. The second MOS transistor is connected through a resistive element to an external power supply node. A voltage produced by the current/voltage converting element is converted into current by a voltage/current converting portion. Thus, constant current free from both vibration and a deadlock phenomenon and with small external power supply voltage dependency is supplied.
摘要翻译： 在第一p沟道MOS晶体管和接地节点之间提供电流源，并且电流/电压转换元件与接地节点和具有足够大的电导系数的第二p沟道MOS晶体管之间的电流源隔离地提供。 的第一MOS晶体管。 第二MOS晶体管通过电阻元件连接到外部电源节点。 由电流/电压转换元件产生的电压由电压/电流转换部分转换成电流。 因此，提供不受振动和死锁现象以及小外部电源电压依赖性的恒定电流。
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公开(公告)号：US07764540B2
公开(公告)日：2010-07-27
申请号：US12281271
申请日：2006-03-01
IPC分类号： G11C11/34
CPC分类号： G11C11/405 , G11C7/18 , G11C11/4097 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON.
摘要翻译： 通过与设置为OFF的存储晶体管并行地激活字线和位线，控制充电线，字线和位线的电位条件，使得身体区域的电位增加一 在存储晶体管导通的期间内，从连接节点流向身体区域的漏电流。
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公开(公告)号：US07738312B2
公开(公告)日：2010-06-15
申请号：US12000343
申请日：2007-12-12
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/12 , G11C7/18 , G11C11/405 , G11C11/4094 , G11C11/4097 , G11C2211/4016 , H01L21/84 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.
摘要翻译： 一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。 第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。 当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。 可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。
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公开(公告)号：US07656736B2
公开(公告)日：2010-02-02
申请号：US11717717
申请日：2007-03-14
IPC分类号： G11C5/14
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
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公开(公告)号：US20090003091A1
公开(公告)日：2009-01-01
申请号：US12201024
申请日：2008-08-29
申请人： Kenji Yoshinaga , Fukashi Morishita
发明人： Kenji Yoshinaga , Fukashi Morishita
CPC分类号： G11C5/147
摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.
摘要翻译： 提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。 控制电路，行/列解码器和读出放大器由内部降压电压驱动。 另一方面，具有高功耗的数据路径由外部电源电压驱动。 电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。 电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据路径。
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公开(公告)号：US07397315B2
公开(公告)日：2008-07-08
申请号：US11311301
申请日：2005-12-20
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , H03K17/063
摘要： The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.
摘要翻译： 本发明提供一种即使在以低电源电压驱动的情况下也能够稳定工作的电流限制型振荡器和使用该振荡器的电荷泵电路。 限流振荡器具有延迟部分，该延迟部分包括多个串联的反相器，用于基于限流电平指示信号来延迟输出脉冲，并且该振荡器还包括至少一个第一晶体管，其限制第一电流 所述逆变器和高电位电源以及限制所述逆变器之间的第二电流和低电位电源的至少一个第二晶体管，其中所述多个逆变器中的至少一个被配置为与所述第一逆变器连接的第一逆变器 并且不与第二晶体管连接，并且多个反相器中的至少另一个被配置为不与第一晶体管连接并与第二晶体管连接的第二反相器。
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公开(公告)号：US20080023764A1
公开(公告)日：2008-01-31
申请号：US11902996
申请日：2007-09-27
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L29/786
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.
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公开(公告)号：US20070247885A1
公开(公告)日：2007-10-25
申请号：US11730969
申请日：2007-04-05
申请人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
IPC分类号： G11C15/00
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。
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公开(公告)号：US07157773B2
公开(公告)日：2007-01-02
申请号：US10330093
申请日：2002-12-30
申请人： Hiroshi Kato , Shigehiro Kuge , Hideyuki Noda , Fukashi Morishita , Shuichi Ueno
发明人： Hiroshi Kato , Shigehiro Kuge , Hideyuki Noda , Fukashi Morishita , Shuichi Ueno
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L21/28282 , H01L29/792
摘要： A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.
摘要翻译： 非易失性半导体存储器件的存储单元通过ONO膜形成在硅衬底上形成的硅层上。 存储单元具有在硅层中形成的源区和漏区，ONO膜和栅电极。 ONO膜和ONO膜包括具有捕获电荷的电荷陷阱部分的氮化物膜。
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公开(公告)号：US07068093B2
公开(公告)日：2006-06-27
申请号：US10336793
申请日：2003-01-06
CPC分类号： G05F3/262
摘要： A voltage adjusting circuit includes a transistor connected in a current mirror, and a resistor element connected to the transistor. The resistor element has a resistance that changes with temperature, so the voltage level is adjusted according to variations in temperature. Accordingly, stable control of an internal circuit in which desirable operating characteristics change with temperature can be attained, even when temperature varies.
摘要翻译： 电压调节电路包括连接在电流镜中的晶体管和连接到晶体管的电阻元件。 电阻元件具有随温度变化的电阻，因此根据温度变化来调整电压电平。 因此，即使在温度变化的情况下，也能够实现期望的工作特性随温度变化的内部电路的稳定控制。
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