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    Memory device and memory data reading method
    41.
    发明申请
    Memory device and memory data reading method 有权
    存储器和存储器数据读取方式

    公开(公告)号：US20090210776A1

    公开(公告)日：2009-08-20

    申请号：US12216744

    申请日：2008-07-10

    申请人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

    发明人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

    摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

    摘要翻译： 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

    DATA STORAGE DEVICE AND PROGRAM METHOD THEREOF
    42.
    发明申请
    DATA STORAGE DEVICE AND PROGRAM METHOD THEREOF 有权
    数据存储设备及其程序方法

    公开(公告)号：US20110276857A1

    公开(公告)日：2011-11-10

    申请号：US13103460

    申请日：2011-05-09

    申请人： Yong June Kim ,  Kyoung Lae Cho ,  Hong Rak Son

    发明人： Yong June Kim ,  Kyoung Lae Cho ,  Hong Rak Son

    IPC分类号： G06F12/00 ,  G06F11/10 ,  H03M13/05

    CPC分类号： G06F11/1048 ,  G11C29/10 ,  G11C2029/0411 ,  H03M7/46

    摘要： A data storage device includes a non-volatile memory device including a plurality of memory cells and a memory controller. The memory controller is configured to modify an arrangement of program data and to program the modified program data into the plurality of memory cells. The memory controller modifies the program data to eliminate a given data pattern causing physical interference between adjacent memory cells from the modified program data.

    摘要翻译： 数据存储装置包括包括多个存储器单元和存储器控制器的非易失性存储器件。 存储器控制器被配置为修改程序数据的布置并且将修改的程序数据编程到多个存储器单元中。 存储器控制器修改程序数据以消除给定的数据模式，从修改的程序数据导致相邻存储器单元之间的物理干扰。

    Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device
    43.
    发明授权
    Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device 有权
    非易失性存储器件，其操作方法以及具有非易失性存储器件的器件

    公开(公告)号：US08508990B2

    公开(公告)日：2013-08-13

    申请号：US13071727

    申请日：2011-03-25

    申请人： Kyoung Lae Cho ,  Hyuck-Sun Kwon ,  Jun Jin Kong

    发明人： Kyoung Lae Cho ,  Hyuck-Sun Kwon ,  Jun Jin Kong

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C16/3454

    摘要： A non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit is configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels.

    摘要翻译： 非易失性存储器件包括存储单元阵列，该存储单元阵列包括多个多电平单元，每个多电平单元存储对应于第一组状态的多种状态之一的数据，以及控制电路。 控制电路被配置为根据第一组验证电压电平的第一验证电压电平对与第一多电平单元中的多个状态中的一个状态相对应的数据，并且将第一多电平单元控制为 根据第二组验证电压电平的第一验证电压电平，将其重新编程为第二组状态的多个状态之一。 第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。

    Memory system with error correction decoder architecture having reduced latency and increased throughput
    44.
    发明授权
    Memory system with error correction decoder architecture having reduced latency and increased throughput 有权
    具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量

    公开(公告)号：US08479085B2

    公开(公告)日：2013-07-02

    申请号：US12191458

    申请日：2008-08-14

    申请人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    发明人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411

    摘要： A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

    摘要翻译： 存储器系统包括：包括纠错解码器的存储器控​​制器。 纠错解码器包括：解复用器，适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器 以及多路复用器，其适于多路复用第一组数据和第二组数据，并将复用的数据提供给误差校正器。 当误差校正器校正第一组数据中的错误时，误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。

    Memory device and method of reading memory data
    46.
    发明申请
    Memory device and method of reading memory data 有权
    存储器件和读取存储器数据的方法

    公开(公告)号：US20090190396A1

    公开(公告)日：2009-07-30

    申请号：US12219264

    申请日：2008-07-18

    申请人： Kyoung Lae Cho ,  Dong Hun Yu ,  Jun Jin Kong ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jong Han Kim ,  Young Hwan Lee

    发明人： Kyoung Lae Cho ,  Dong Hun Yu ,  Jun Jin Kong ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jong Han Kim ,  Young Hwan Lee

    IPC分类号： G11C16/06 ,  G11C7/00

    CPC分类号： G11C16/34 ,  G11C11/5642 ,  G11C2211/5634

    摘要： A memory device and a method of reading multi-bit data stored in a multi-bit cell array may be provided. The memory device may include a multi-bit cell array including a least one memory page with each memory page having a plurality of multi-bit cells, and a determination unit to divide the plurality of multi-bit cells into a first group and second group. The first group may include multi-bit cells with a threshold voltage higher than a reference voltage. The second group may include multi-bit cells with a threshold voltage lower than the reference voltage. The determination unit may sequentially update the first group and second group while changing the reference voltage.

    摘要翻译： 可以提供存储器件和读取存储在多位单元阵列中的多位数据的方法。 存储器件可以包括多比特单元阵列，其包括至少一个存储器页，每个存储器页具有多个多位单元，以及确定单元，用于将多个多位单元划分成第一组和第二组 。 第一组可以包括具有高于参考电压的阈值电压的多位单元。 第二组可以包括阈值电压低于参考电压的多位单元。 确定单元可以在改变参考电压的同时顺序地更新第一组和第二组。

    Apparatus and method for multi-bit programming
    47.
    发明申请
    Apparatus and method for multi-bit programming 审中-公开
    多位编程的装置和方法

    公开(公告)号：US20090046510A1

    公开(公告)日：2009-02-19

    申请号：US12007775

    申请日：2008-01-15

    申请人： Seung-Hwan Song ,  Jun Jin Kong ,  Sung Chung Park ,  Heeseok Eun ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    发明人： Seung-Hwan Song ,  Jun Jin Kong ,  Sung Chung Park ,  Heeseok Eun ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    IPC分类号： G11C7/10

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

    摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell.

    摘要翻译： 提供了多位编程设备和方法。 一种多位编程设备可以包括：第一编程单元，其存储对应于可连接到至少一个第一位线的至少一个第一存储器单元中的多个第一位的数据; 以及第二编程单元，其将可能连接到至少一个第二位线的至少一个第二存储器单元中的与第二位数相对应的数据存储。 由此，可以提高数据可靠性并增加要存储在整个存储单元中的位数。

    DATA COMPRESSION DEVICES, OPERATING METHODS THEREOF, AND DATA PROCESSING APPARATUSES INCLUDING THE SAME
    50.
    发明申请
    DATA COMPRESSION DEVICES, OPERATING METHODS THEREOF, AND DATA PROCESSING APPARATUSES INCLUDING THE SAME 有权
    数据压缩装置，其操作方法和包括其的数据处理装置

    公开(公告)号：US20120182163A1

    公开(公告)日：2012-07-19

    申请号：US13353984

    申请日：2012-01-19

    申请人： Kyoung Lae Cho ,  Chan Ho Yoon ,  Jun Jin Kong ,  Pil Sang Yoon

    发明人： Kyoung Lae Cho ,  Chan Ho Yoon ,  Jun Jin Kong ,  Pil Sang Yoon

    IPC分类号： H03M7/30

    CPC分类号： H03M7/30 ,  H03M7/6088

    摘要： A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

    摘要翻译： 操作数据压缩装置的方法包括使用分析器分析数据并产生分析结果，同时数据由输入缓冲器缓冲，并根据分析结果选择性地压缩缓冲的数据。 数据压缩装置包括数据模式分析器，被配置为分析发送到输入缓冲器的数据，并且基于数据的分析生成分析代码; 以及数据压缩管理器，被配置为基于分析代码选择性地压缩输入缓冲器中的数据。