公开(公告)号：US20060007770A1

公开(公告)日：2006-01-12

申请号：US10968811

申请日：2004-10-20

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

摘要翻译： 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

公开(公告)号：US06707740B2

公开(公告)日：2004-03-16

申请号：US10103872

申请日：2002-03-25

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C700

CPC分类号： G11C7/106 ,  G11C7/06 ,  G11C7/103 ,  G11C7/1069 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/065

摘要： A plurality of sense amplifiers amplify parallel read data from memory cells, respectively. At least one of read amplifiers for amplifying the amplified read data respectively has a higher drivability than those of the rest of the read amplifiers. A connection switching circuit connects the sense amplifiers to a predetermined read amplifier according to an address. Switching the read data to one another before the amplification by the read amplifiers allows read data to be first outputted in burst read operation to be amplified by the read amplifier whose drivability is always high. In the burst read operation, a data output circuit first outputs read data corresponding to the read amplifier whose drivability is high. This enables reductions in read operation time and power consumption, even in a semiconductor memory in which the output orders of read data are changeable according to addresses or operation modes.

摘要翻译： 多个读出放大器分别从存储器单元放大并行读取数据。 用于放大放大的读取数据的读取放大器中的至少一个分别具有比其余的读取放大器更高的驾驶性能。 连接切换电路根据地址将读出放大器连接到预定的读取放大器。 在读取放大器的放大之前将读取的数据切换到彼此之后，允许首先在突发读取操作中输出读取数据，以便其驱动能力始终为高的读取放大器放大。 在突发读取操作中，数据输出电路首先输出对应于驱动能力高的读取放大器的读取数据。 即使在读取数据的输出顺序根据地址或操作模式而变化的半导体存储器中，也能够降低读取操作时间和功耗。

公开(公告)号：US06480033B2

公开(公告)日：2002-11-12

申请号：US09317619

申请日：1999-05-25

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： H03K19094

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/22 ,  H03K3/356139

摘要： A semiconductor integrated circuit including a semiconductor device has a command decoder unit for decoding command signals synchronously with an external clock. An internal signal whose timing precedes the timing of the command decoder unit decoding the command signals is used to reset the command decoder unit. Preferably, a signal produced by a DLL is used as the internal signal. Consequently, a margin in timing of actuating the semiconductor device is expanded.

摘要翻译： 包括半导体器件的半导体集成电路具有用于与外部时钟同步地解码命令信号的命令解码器单元。 在命令解码器单元解码命令信号的定时之前的定时的内部信号用于复位命令解码器单元。 优选地，由DLL产生的信号用作内部信号。 因此，促进半导体器件的定时裕度扩大。

公开(公告)号：US06337819B1

公开(公告)日：2002-01-08

申请号：US09551570

申请日：2000-04-18

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C700

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/5004

摘要： A step-down circuit 10A comprises a voltage follower circuit 20A for receiving a voltage VG, to be measured, of an internal circuit, activated in response to activation of a test mode signal TM, and providing its output to an on-chip pad 16A. Although a large current flows through an output buffer circuit 22 of the voltage follower circuit 20A compared with that of an output buffer circuit 15 of a voltage control circuit 12, this large current does not flow when the signal TM is inactive. The voltage follower circuit having a comparatively large area on chip can commonly be used with a selection circuit for selecting one of nodes with voltages to be measured. In a case of SDRAM, the signal TM may be an output of the command decoder and a selection control signal may be an address signal.

摘要翻译： 降压电路10A包括电压跟随器电路20A，用于接收被测量的内部电路的电压VG，响应于测试模式信号TM的激活而激活，并将其输出提供给片上焊盘16A 。 虽然与电压控制电路12的输出缓冲电路15相比，大电流流过电压跟随器电路20A的输出缓冲器电路22，但是当信号TM不活动时，该大电流不流动。 具有比较大的芯片面积的电压跟随器电路通常可以与用于选择要测量的电压的节点之一的选择电路一起使用。 在SDRAM的情况下，信号TM可以是命令解码器的输出，并且选择控制信号可以是地址信号。

公开(公告)号：US06212092B1

公开(公告)日：2001-04-03

申请号：US09533886

申请日：2000-03-22

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C506

CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/225 ,  G11C11/401 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

摘要： The semiconductor integrated circuit comprises a memory cell, a sense amplifier, input/output controlling circuit, a switch circuit which connects the sense amplifier and the input/output circuit, a reference timing signal generator, a timing controlling circuit having a delay element, and a switch controlling circuit which controls the switch circuit. The reference timing signal generator generates a reference timing signal necessary for read/write operations. The timing controlling circuit receives the reference timing signal and generates, by using the delay element thereof, at least one of either a read controlling signal or a write controlling signal whose timing shifts from the timing of the switch controlling signal by a predetermined amount of time. Therefore, the deviation between the timings of the switch controlling signal and the read controlling signal or the write controlling signal can easily be set to a predetermined value. The timing deviation is not easily affected by fluctuations occurring in a manufacturing process, an operation voltage, or ambient temperature. Therefore, it is possible to carry out the timing design to minimize the deviation between the timings of the switch controlling signal and the read controlling signal or the write controlling signal. As a result, a high-speed operation can be performed. When the high-speed operation is not pursued, it is possible to increase timing margins of other circuits so that the yield improves.

摘要翻译： 半导体集成电路包括存储单元，读出放大器，输入/输出控制电路，连接读出放大器和输入/输出电路的开关电路，基准定时信号发生器，具有延迟元件的定时控制电路，以及 控制开关电路的开关控制电路。 参考定时信号发生器产生读/写操作所需的参考定时信号。 定时控制电路接收参考定时信号，并且通过使用其延迟元件来生成定时从开关控制信号的定时偏移预定时间量的读控制信号或写控制信号中的至少一个 。 因此，切换控制信号的定时与读取控制信号或写入控制信号之间的偏差可以容易地设定为预定值。 定时偏差不容易受到在制造过程，操作电压或环境温度下发生的波动的影响。 因此，可以执行定时设计以最小化开关控制信号的定时与读控制信号或写控制信号之间的偏差。 结果，可以执行高速操作。 当不追求高速运行时，可以提高其他电路的定时裕度，从而提高产量。

公开(公告)号：US6084802A

公开(公告)日：2000-07-04

申请号：US22492

申请日：1998-02-12

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C11/413 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C16/04

CPC分类号： G11C7/1039 ,  G11C7/22

摘要： A pipe-line control of internal circuits is performed by an internal clock whose timing does not depend on a predetermined phase difference to the phase of an external clock. To control the timing of the output signal from an output circuit to the predetermined phase difference with respect to the phase of the external clock, a delay circuit is inserted at the subsequent stage of the last stage of pipe-line gate. The delay time of this delay circuit is so controlled as to set the timing of the output signal to have the predetermined phase difference to the phase of the external clock.

摘要翻译： 内部电路的管线控制由其定时不依赖于与外部时钟的相位的预定相位差的内部时钟来执行。 为了控制输出电路的输出信号相对于外部时钟的相位的预定相位差的定时，在管线门的最后一级的后续阶段插入延迟电路。 该延迟电路的延迟时间被如此控制，以将输出信号的定时设定为与外部时钟的相位具有预定的相位差。

公开(公告)号：US5990730A

公开(公告)日：1999-11-23

申请号：US107138

申请日：1998-06-30

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/08 ,  G06F1/32

CPC分类号： G11C11/4076 ,  G11C11/4072 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/04

摘要： A semiconductor device which performs a predetermined operation includes a timing-stabilization circuit which performs a timing adjustment with respect to an internal clock signal, and a current-consumption circuit which consumes a predetermined amount of a current so as to emulate conditions of such current consumption as would be observed during the predetermined operation of the semiconductor device. The semiconductor device further includes a start-up-period control circuit which makes the timing-stabilization circuit and the current-consumption circuit operate at a beginning of power supply so as to perform the timing adjustment under the conditions, and stops operations of the timing-stabilization circuit and the current-consumption circuit after completion of the timing adjustment.

摘要翻译： 执行预定操作的半导体器件包括对内部时钟信号执行定时调整的定时稳定电路和消耗预定量的电流的电流消耗电路，以便模拟这种电流消耗的条件 如在半导体器件的预定操作期间将观察到的那样。 半导体装置还包括启动周期控制电路，其使定时稳定电路和电流消耗电路在电源开始时工作，以在条件下执行定时调整，并停止定时的操作 稳定电路和完成定时调整后的电流消耗电路。

公开(公告)号：US5861648A

公开(公告)日：1999-01-19

申请号：US917748

申请日：1997-08-27

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： H01L27/04 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H02M3/07 ,  H03K19/00 ,  H01L29/40

CPC分类号： H02M3/073

摘要： A booster circuit is used to boost a first voltage using a capacitor unit so as to generate a second voltage. The capacitor unit has at least one MOS capacitor each formed by a MOS transistor, and at least one conductive electrode capacitor, each connected in parallel with corresponding MOS capacitor. Each conductive electrode capacitor includes a first conductive electrode and a second conductive electrode which are mutually opposed, and a dielectric layer interposed between the first and second conductive electrodes. Therefore, the low-voltage operating point margin of the booster circuit can be expanded while an increase in the area occupied by the booster circuit is suppressed.

摘要翻译： 升压电路用于使用电容器单元来升高第一电压，以产生第二电压。 电容器单元具有由MOS晶体管形成的至少一个MOS电容器和至少一个导电电极电容器，每个导体电极电容器与相应的MOS电容器并联连接。 每个导电电极电容器包括彼此相对的第一导电电极和第二导电电极，以及介于第一和第二导电电极之间的电介质层。 因此，可以扩大升压电路的低电压工作点余量，同时抑制升压电路占用面积的增加。

公开(公告)号：US5841731A

公开(公告)日：1998-11-24

申请号：US862298

申请日：1997-05-22

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G11C8/00

CPC分类号： G11C7/1045

摘要： A semiconductor device which allows an input signal thereto to select one of N operation modes, and operates in the one of N operation modes includes a selection circuit for selecting an operation mode from the N operation modes when the input signal indicates the operation mode, and for selecting a predetermined operation mode from the N operation modes when the input signal is an undefined signal indicating none of the N operation modes. The semiconductor device further includes an internal circuit operating in an operation mode selected by the selection circuit.

摘要翻译： 允许其输入信号选择N个操作模式之一并且以N个操作模式中的一个操作的半导体器件包括用于当输入信号指示操作模式时从N个操作模式中选择操作模式的选择电路，以及 用于当输入信号是指示N种操作模式的未定义信号时，从N种操作模式中选择预定的操作模式。 半导体器件还包括以由选择电路选择的操作模式工作的内部电路。

公开(公告)号：US5729500A

公开(公告)日：1998-03-17

申请号：US789803

申请日：1997-01-28

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C11/407 ,  G11C7/00 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C11/4076 ,  G11C7/22

摘要： A DRAM to which a setting can be made to determine an internal operation frequency thereof includes a memory cell array, sense amplifiers writing data to and reading data from the memory cell array, a pair of data-bus lines, and gates connecting between the pair of data-bus lines and the sense amplifiers, the gates providing the pair of data-bus lines with access to the sense amplifiers when the gates are open. The DRAM further includes a control circuit controlling a period of the access to be a different period for a different setting of the internal operation frequency.

摘要翻译： 可以进行设置以确定其内部操作频率的DRAM包括存储单元阵列，读取数据和从存储单元阵列读取数据的读出放大器，一对数据总线和连接在该对之间的门 的数据总线和读出放大器，当门打开时，门提供一对数据总线与读出放大器的访问。 DRAM还包括一个控制电路，用于控制对于内部操作频率的不同设置的访问周期为不同的周期。