利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

178 条记录 (耗时 0.031 秒)

    One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell
    42.
    发明申请
    One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell 有权
    一个晶体管/一个电容器动态随机存取存储器（1T / 1C DRAM）单元

    公开(公告)号：US20090166701A1

    公开(公告)日：2009-07-02

    申请号：US12006061

    申请日：2007-12-28

    申请人： Brian S. Doyle ,  Dinesh Somasekhar ,  Robert S. Chau

    发明人： Brian S. Doyle ,  Dinesh Somasekhar ,  Robert S. Chau

    IPC分类号： H01L27/108 ,  H01L21/8248

    CPC分类号： H01L28/87 ,  H01L27/10852

    摘要： In general, in one aspect, a method includes forming a semiconductor fin. A first insulating layer is formed adjacent to the semiconductor fin. A second insulating layer is formed over the first insulating layer and the semiconductor fin. A first trench is formed in the second insulating layer and the first insulating layer therebelow. The first trench is filed with a polymer. A third insulating layer is formed over the polymer. A second trench is formed in the third insulating layer, wherein the second trench is above the first trench and extends laterally therefrom. The polymer is removed from the first trench. A capacitor is formed within the first and the second trenches.

    摘要翻译： 通常，一方面，一种方法包括形成半导体鳍片。 第一绝缘层邻近半导体鳍形成。 在第一绝缘层和半导体鳍上形成第二绝缘层。 在第二绝缘层和第一绝缘层中形成第一沟槽。 第一个沟槽与聚合物一起提交。 在聚合物上形成第三绝缘层。 第二沟槽形成在第三绝缘层中，其中第二沟槽在第一沟槽之上并且从其横向延伸。 从第一沟槽去除聚合物。 在第一和第二沟槽内形成电容器。

    Capacitor, method of increasing a capacitance area of same, and system containing same
    43.
    发明申请
    Capacitor, method of increasing a capacitance area of same, and system containing same 有权
    电容器，增加电容面积相同的方法，以及包含其的系统

    公开(公告)号：US20080237675A1

    公开(公告)日：2008-10-02

    申请号：US11731543

    申请日：2007-03-29

    申请人： Brian S. Doyle ,  Roberts S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

    发明人： Brian S. Doyle ,  Roberts S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

    IPC分类号： H01L27/108 ,  H01L21/20 ,  H01L29/92

    CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L29/785

    摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

    摘要翻译： 电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。 第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。 第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。 第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。 在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

    Memory cell without halo implant
    46.
    发明授权
    Memory cell without halo implant 有权
    无光晕植入的记忆细胞

    公开(公告)号：US07355246B2

    公开(公告)日：2008-04-08

    申请号：US11268430

    申请日：2005-11-07

    申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    IPC分类号： H01L29/76

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

    摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

    摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

    APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY
    49.
    发明申请
    APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY 失效
    用于编程存储阵列的装置和方法

    公开(公告)号：US20060285393A1

    公开(公告)日：2006-12-21

    申请号：US11158518

    申请日：2005-06-21

    申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

    发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

    IPC分类号： G11C16/04

    CPC分类号： G11C17/18

    摘要： A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

    摘要翻译： 提供了一种对存储器阵列进行编程的方法，包括通过相对于各个字线相互依次提供多个电压步骤来访问存储器阵列的多个字线，以及每个存储器阵列的多个位线 访问相应字线的时间，对与同时访问的各个字和位线相对应的多个设备进行编程，每个设备通过断开设备的介电层进行编程，访问位线被排序，使得只有 一个设备中的单个设备一次被编程。

    Purge-based floating body memory
    50.
    发明申请
    Purge-based floating body memory 有权
    基于清洗的浮体记忆

    公开(公告)号：US20060279985A1

    公开(公告)日：2006-12-14

    申请号：US11151982

    申请日：2005-06-14

    申请人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De ,  Gerhard Schrom

    发明人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De ,  Gerhard Schrom

    IPC分类号： G11C11/34

    CPC分类号： G11C11/404 ,  G11C2211/4016

    摘要： In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.

    摘要翻译： 通常，在一个方面，本公开描述了包括以行和列布置的多个存储单元的存储器阵列。 每个存储单元包括具有能够存储电荷的浮动体的晶体管。 多个字线和清除线与存储器单元的行互连。 多个位线被连接到存储器单元的列。 通过字线提供的驱动信号，清除线和位线可以协作以改变一个或多个存储器单元中的浮体区域的电荷。