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公开(公告)号：US11984855B2
公开(公告)日：2024-05-14
申请号：US17314836
申请日：2021-05-07
Applicant: pSemi Corporation
Inventor： Emre Ayranci , Miles Sanner
CPC classification number: H03F1/0277 , H03F1/086 , H03F1/565 , H03F3/193 , H03F3/195 , H03F3/72 , H03F2200/111 , H03F2200/18 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/252 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/321 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/411 , H03F2200/42 , H03F2200/429 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H03F2203/7206 , H03F2203/7209 , H03F2203/7233
Abstract: A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.
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公开(公告)号：US11848648B2
公开(公告)日：2023-12-19
申请号：US17573375
申请日：2022-01-11
Applicant: pSemi Corporation
Inventor： Kashish Pal , Emre Ayranci , Miles Sanner
CPC classification number: H03F1/223 , H03F1/26 , H03F3/193 , H03F3/68 , H04L27/2647 , H03F1/0277 , H03F2200/294 , H03F2200/489
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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公开(公告)号：US11804816B2
公开(公告)日：2023-10-31
申请号：US17669789
申请日：2022-02-11
Applicant: pSemi Corporation
Inventor： Emre Ayranci , Miles Sanner , Ke Li , James Francis McElwee , Tero Tapio Ranta , Kevin Roberts , Chih-Chieh Cheng
IPC: H04B1/04 , H04B1/40 , H01B1/00 , H04W88/06 , H03H7/38 , H03H7/01 , H04B1/00 , H04W72/0453 , H04W28/06 , H04L5/00
CPC classification number: H03H7/0161 , H04B1/006 , H04B1/0053 , H04B1/0067 , H04W72/0453 , H03H7/38 , H03H2210/033 , H03H2210/036 , H04L5/001 , H04W28/065
Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability. In a third version, CA direct mapped adaptive tuning networks include filter tuning blocks for selected lower frequency bands.
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公开(公告)号：US20220345096A1
公开(公告)日：2022-10-27
申请号：US17741130
申请日：2022-05-10
Applicant: pSemi Corporation
Inventor： Emre Ayranci , Miles Sanner , Phanindra Yerramilli
Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
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公开(公告)号：US20220209719A1
公开(公告)日：2022-06-30
申请号：US17573375
申请日：2022-01-11
Applicant: pSemi Corporation
Inventor： Kashish Pal , Emre Ayranci , Miles Sanner
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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Patent Agency Ranking
公开(公告)号：US11336243B2
公开(公告)日：2022-05-17
申请号：US17010311
申请日：2020-09-02
Applicant: pSemi Corporation
Inventor： Emre Ayranci , Miles Sanner , Phanindra Yerramilli
Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
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公开(公告)号：US20210058044A1
公开(公告)日：2021-02-25
申请号：US17010311
申请日：2020-09-02
Applicant: pSemi Corporation
Inventor： Emre Ayranci , Miles Sanner , Phanindra Yerramilli
Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
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48.发明申请公开(公告)号：US20200328724A1
公开(公告)日：2020-10-15
申请号：US16860739
申请日：2020-04-28
Applicant: pSemi Corporation
Inventor： Emre Ayranci , Miles Sanner
Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
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49.发明申请公开(公告)号：US20190372528A1
公开(公告)日：2019-12-05
申请号：US15991980
申请日：2018-05-29
Applicant: pSemi Corporation
Inventor： Kashish Pal , Emre Ayranci , Miles Sanner
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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公开(公告)号：US10250199B2
公开(公告)日：2019-04-02
申请号：US15268229
申请日：2016-09-16
Applicant: pSemi Corporation
Inventor： Jonathan Klaren , Poojan Wagh , David Kovac , Eric S. Shapiro , Neil Calanca , Dan William Nobbe , Christopher Murphy , Robert Mark Englekirk , Emre Ayranci , Keith Bargroff , Tero Tapio Ranta
Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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