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公开(公告)号：US20230152836A1
公开(公告)日：2023-05-18
申请号：US17987722
申请日：2022-11-15
Applicant: pSemi Corporation
Inventor： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta
Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.
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公开(公告)号：US11374540B2
公开(公告)日：2022-06-28
申请号：US16935999
申请日：2020-07-22
Applicant: pSemi Corporation
Inventor： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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公开(公告)号：US20220065723A1
公开(公告)日：2022-03-03
申请号：US17467251
申请日：2021-09-05
Applicant: pSemi Corporation
Inventor： Vishnu Srinivasan , Ion Opris , Keith Bargroff
Abstract: Methods and devices to mitigate time varying impairments in sensors are described. The application of such methods and devices to pressure sensors facing time varying parasitic capacitances due to water droplets is detailed. Benefits of auto-zeroing technique as adopted in disclosed devices is also described.
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公开(公告)号：US11251140B2
公开(公告)日：2022-02-15
申请号：US16875615
申请日：2020-05-15
Applicant: pSemi Corporation
Inventor： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta , Simon Edward Willard
IPC: H03B1/00 , H03K3/00 , H01L23/60 , H01L27/12 , H01L29/786 , H03K17/687 , H01L23/552 , H01L29/10 , H01L23/66 , H03K17/0412 , H01L21/762 , H03K17/0416 , H03K17/042 , H03K17/14
Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.
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公开(公告)号：US20210013841A1
公开(公告)日：2021-01-14
申请号：US16935999
申请日：2020-07-22
Applicant: pSemi Corporation
Inventor： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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Patent Agency Ranking
公开(公告)号：US20200218304A1
公开(公告)日：2020-07-09
申请号：US16732619
申请日：2020-01-02
Applicant: pSemi Corporation
Inventor： Harish Raghavan , Keith Bargroff , Anan Xiang
IPC: G05F3/26
Abstract: Systems, methods, and apparatus for practical realization of a current source with a programmable temperature profile are described. The temperature profile can include profile segments with different programmable slopes. Programmable slopes of any one of the profile segments can be according to any of a ZTAT, PTAT and CTAT profiles. When integrated in an electronic device, the programmable temperature profile can be used statically with a pre-programmed configuration and optionally fused profile, or dynamically to control a performance of the electronic device via adjustments of the temperature profile.
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公开(公告)号：US10546747B2
公开(公告)日：2020-01-28
申请号：US16167424
申请日：2018-10-22
Applicant: pSemi Corporation
Inventor： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta , Simon Edward Willard
IPC: H01L29/06 , H01L21/02 , H01L21/8234 , H01L21/322 , H01L21/265 , H01L21/762 , H01L27/12
Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).
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公开(公告)号：US10439563B2
公开(公告)日：2019-10-08
申请号：US15908469
申请日：2018-02-28
Applicant: pSemi Corporation
Inventor： Tsuyoshi Takagi , Tero Tapio Ranta , Keith Bargroff , Christopher C. Murphy , Robert Mark Englekirk
Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. Other embodiments include bias compensation circuits that directly regulate a bias signal to an amplifier stage as a function of localized heating of one or more of amplifier stages. Such bias compensation circuits include physical placement of at least one bias compensation circuit element in closer proximity to at least one amplifier stage than other bias compensation circuit elements. One bias compensation circuit embodiment includes a temperature-sensitive current mirror circuit for regulating the bias signal. Another bias compensation circuit embodiment includes a temperature-sensitive element having a positive temperature coefficient (PTC) for regulating the bias signal.
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公开(公告)号：US20190158029A1
公开(公告)日：2019-05-23
申请号：US16240601
申请日：2019-01-04
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US20190121383A1
公开(公告)日：2019-04-25
申请号：US15793943
申请日：2017-10-25
Applicant: pSemi Corporation
Inventor： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta
Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.
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