公开(公告)号：US20240347482A1

公开(公告)日：2024-10-17

申请号：US18614372

申请日：2024-03-22

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H01L23/60 ,  H01L21/762 ,  H01L23/552 ,  H01L23/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H03K17/0412 ,  H03K17/0416 ,  H03K17/042 ,  H03K17/14 ,  H03K17/687

CPC classification number: H01L23/60 ,  H01L21/76264 ,  H01L23/552 ,  H01L23/66 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1218 ,  H01L29/1095 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78618 ,  H03K17/04123 ,  H03K17/04163 ,  H03K17/04206 ,  H03K17/145 ,  H03K17/6872

Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

公开(公告)号：US20240288476A1

公开(公告)日：2024-08-29

申请号：US18534003

申请日：2023-12-08

Applicant: pSemi Corporation

Inventor： Damian Costa ,  Chih-Chieh Cheng ,  Christopher C. Murphy ,  Tero Tapio Ranta

IPC: G01R19/25 ,  G01R31/40 ,  H03F1/02 ,  H04B10/079

CPC classification number: G01R19/2513 ,  H03F1/0211 ,  H04B10/07955 ,  G01R31/40

Abstract: A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation. In one aspect, active resistors are used in order to compensate for temperature variations.

公开(公告)号：US11955932B2

公开(公告)日：2024-04-09

申请号：US18322166

申请日：2023-05-23

Applicant: pSemi Corporation

Inventor： Jonathan James Klaren ,  David Kovac ,  Eric S. Shapiro ,  Christopher C. Murphy ,  Robert Mark Englekirk ,  Keith Bargroff ,  Tero Tapio Ranta

IPC: H03F1/22 ,  H03F1/30 ,  H03F1/56 ,  H03F3/19 ,  H03F3/193 ,  H03F3/195 ,  H03F3/213 ,  H03F3/24

CPC classification number: H03F1/223 ,  H03F1/301 ,  H03F1/56 ,  H03F3/193 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/105 ,  H03F2200/165 ,  H03F2200/18 ,  H03F2200/21 ,  H03F2200/222 ,  H03F2200/225 ,  H03F2200/243 ,  H03F2200/294 ,  H03F2200/297 ,  H03F2200/301 ,  H03F2200/306 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/399 ,  H03F2200/42 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/498 ,  H03F2200/555 ,  H03F2200/61 ,  H03F2200/78

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

公开(公告)号：US11948897B2

公开(公告)日：2024-04-02

申请号：US17669812

申请日：2022-02-11

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H01L23/60 ,  H01L21/762 ,  H01L23/552 ,  H01L23/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H03K17/0412 ,  H03K17/0416 ,  H03K17/042 ,  H03K17/14 ,  H03K17/687

CPC classification number: H01L23/60 ,  H01L21/76264 ,  H01L23/552 ,  H01L23/66 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1218 ,  H01L29/1095 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78618 ,  H03K17/04123 ,  H03K17/04163 ,  H03K17/04206 ,  H03K17/145 ,  H03K17/6872

Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

公开(公告)号：US20220246550A1

公开(公告)日：2022-08-04

申请号：US17669812

申请日：2022-02-11

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H01L23/60 ,  H01L27/12 ,  H01L29/786 ,  H03K17/687 ,  H01L23/552 ,  H01L29/10 ,  H01L23/66 ,  H03K17/0412 ,  H01L21/762 ,  H03K17/0416 ,  H03K17/042 ,  H03K17/14

Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

公开(公告)号：US20200007088A1

公开(公告)日：2020-01-02

申请号：US16264106

申请日：2019-01-31

Applicant: pSemi Corporation

Inventor： Tero Tapio Ranta ,  Christopher C. Murphy ,  Jeffrey A. Dykstra

IPC: H03F1/22 ,  H03F1/56 ,  H03F3/195 ,  H03F3/16

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.

公开(公告)号：US20190173433A1

公开(公告)日：2019-06-06

申请号：US16253115

申请日：2019-01-21

Applicant: pSemi Corporation

Inventor： Tero Tapio Ranta ,  Keith Bargroff ,  Christopher C. Murphy ,  Robert Mark Englekirk

IPC: H03F1/30 ,  H03F1/56 ,  H03F3/24 ,  H03F3/195 ,  H03F3/213 ,  G05F3/26 ,  H03F3/45

CPC classification number: H03F1/30 ,  G05F3/26 ,  H03F1/56 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F3/45076 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/447 ,  H03F2200/451 ,  H03F2200/462 ,  H03F2200/468 ,  H03F2200/471 ,  H03F2200/474 ,  H03F2203/45596

Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

公开(公告)号：US10305433B2

公开(公告)日：2019-05-28

申请号：US15908533

申请日：2018-02-28

Applicant: pSemi Corporation

Inventor： Tero Tapio Ranta ,  Keith Bargroff ,  Christopher C. Murphy ,  Robert Mark Englekirk

IPC: H03F1/30 ,  H03F3/213 ,  H03F3/195 ,  H03F3/45 ,  G05F3/26 ,  H03F1/56 ,  H03F3/24

Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

公开(公告)号：US20180262164A1

公开(公告)日：2018-09-13

申请号：US15908533

申请日：2018-02-28

Applicant: pSemi Corporation

Inventor： Tero Tapio Ranta ,  Keith Bargroff ,  Christopher C. Murphy ,  Robert Mark Englekirk

IPC: H03F1/30 ,  H03F3/213 ,  H03F3/195 ,  H03F3/45

CPC classification number: H03F1/30 ,  G05F3/26 ,  H03F1/56 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F3/45076 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/447 ,  H03F2200/451 ,  H03F2200/462 ,  H03F2200/468 ,  H03F2200/471 ,  H03F2200/474 ,  H03F2203/45596

Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

公开(公告)号：US20240402749A1

公开(公告)日：2024-12-05

申请号：US18736150

申请日：2024-06-06

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta

IPC: G05F3/26 ,  G05F3/24 ,  H03M1/66 ,  H03M1/74

Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.