公开(公告)号：US20240250157A1

公开(公告)日：2024-07-25

申请号：US18099366

申请日：2023-01-20

申请人： GlobalFoundries U.S. Inc.

发明人： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Yves T. NGU ,  Johnatan A. KANTAROVSKY ,  Sebastian T. VENTRONE

IPC分类号： H01L29/73 ,  H01L23/34 ,  H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/737

CPC分类号： H01L29/7302 ,  H01L23/345 ,  H01L27/075 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/737

摘要： The present disclosure relates to semiconductor structures and, more particularly, to heater terminal contacts, methods of operation and methods of manufacture. The structure includes: a heterojunction bipolar transistor having a collector, sub-collector region, emitter and base region; and heater terminal contacts electrically coupled to the sub-collector region.

公开(公告)号：US09041120B2

公开(公告)日：2015-05-26

申请号：US13950813

申请日：2013-07-25

申请人： Infineon Technologies AG

发明人： Stephan Voss ,  Peter Tuerkes ,  Holger Huesken

IPC分类号： H01L21/70 ,  H01L27/11 ,  H01L29/02 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L29/435 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/075 ,  H03K17/127 ,  H03K17/168

摘要： A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

摘要翻译： 晶体管器件包括：布置在半导体本体上的晶体管单元场中的至少一个单独的晶体管单元，每个单独的晶体管单元包括栅电极; 栅极接触，电耦合到晶体管单元的栅极，并且被配置为通过在第一方向上提供栅极电流并且被配置为通过提供栅极电流来关断所述至少一个晶体管单元来接通所述至少一个晶体管单元 在第二方向上，所述第二方向与所述第一方向相反; 至少一个单片集成在晶体管器件中的栅极电阻器结构，栅极电阻器结构在栅极电流沿第一方向流动时为栅极电流提供第一电阻，并为栅极电流提供不同的第二电阻 当第一电阻时，栅极电流沿第二方向流动。

公开(公告)号：US08878241B2

公开(公告)日：2014-11-04

申请号：US14132021

申请日：2013-12-18

申请人： Macronix International Co., Ltd.

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L21/8222 ,  H01L27/02 ,  H01L49/02 ,  H01L27/07

CPC分类号： H01L21/8222 ,  H01L27/027 ,  H01L27/075 ,  H01L28/20

摘要： A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

公开(公告)号：US20140247651A1

公开(公告)日：2014-09-04

申请号：US14275103

申请日：2014-05-12

申请人： Shuichi Tsukada ,  Yasuhiro Uchiyama

发明人： Shuichi Tsukada ,  Yasuhiro Uchiyama

IPC分类号： G11C11/39 ,  G11C11/4091 ,  G11C11/40

CPC分类号： G11C11/39 ,  G11C11/40 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/411 ,  H01L27/075 ,  H01L27/1021 ,  H01L27/1023 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L28/91 ,  H01L29/7841

摘要： A semiconductor device includes a word line, a bit line, a power supply node, a memory element that includes at least first and second regions that form a PN junction between the bit lie and the power supply node, and a third region that forms a PN junction with the second region and a capacitor that includes a first electrode provided independently from the second region of the memory element and electrically connected to the second region of the memory element, and a second electrode connected to the word line.

摘要翻译： 半导体器件包括字线，位线，电源节点，至少包括在位位和电源节点之间形成PN结的第一和第二区域的存储元件，以及形成第 PN结和电容器，其包括独立于存储元件的第二区域设置并电连接到存储元件的第二区域的第一电极和连接到字线的第二电极。

公开(公告)号：US08648386B2

公开(公告)日：2014-02-11

申请号：US13222187

申请日：2011-08-31

申请人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L27/07

CPC分类号： H01L21/8222 ,  H01L27/027 ,  H01L27/075 ,  H01L28/20

摘要： A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

摘要翻译： 提供其半导体结构及其制造方法以及ESD电路。 半导体结构包括第一掺杂区，第二掺杂区，第三掺杂区和电阻。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性。 第三掺杂区域具有第一类型的导电性。 第一掺杂区域和第三掺杂区域被第二掺杂区域分开。 电阻器耦合在第二掺杂区域和第三掺杂区域之间。 阳极耦合到第一掺杂区域。 阴极耦合到第三掺杂区域。

公开(公告)号：US20130049067A1

公开(公告)日：2013-02-28

申请号：US13222187

申请日：2011-08-31

申请人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Hsin-Liang Chen ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L27/07 ,  H01L21/331

CPC分类号： H01L21/8222 ,  H01L27/027 ,  H01L27/075 ,  H01L28/20

摘要： A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

摘要翻译： 提供其半导体结构及其制造方法以及ESD电路。 半导体结构包括第一掺杂区，第二掺杂区，第三掺杂区和电阻。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性。 第三掺杂区域具有第一类型的导电性。 第一掺杂区域和第三掺杂区域被第二掺杂区域分开。 电阻器耦合在第二掺杂区域和第三掺杂区域之间。 阳极耦合到第一掺杂区域。 阴极耦合到第三掺杂区域。

公开(公告)号：US20030205735A1

公开(公告)日：2003-11-06

申请号：US10442911

申请日：2003-05-21

发明人： Tomotaka Fujisawa ,  Chihiro Arai

IPC分类号： H01L031/0328

CPC分类号： H01L27/075 ,  H01L27/0761

摘要： In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an Nnull sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.

公开(公告)号：US5023482A

公开(公告)日：1991-06-11

申请号：US733416

申请日：1985-05-13

申请人： Joseph T. Bellavance

发明人： Joseph T. Bellavance

IPC分类号： H01L27/02 ,  H01L27/07 ,  H03K19/018 ,  H03K19/091

CPC分类号： H01L27/075 ,  H01L27/0233 ,  H01L27/0244 ,  H03K19/01806 ,  H03K19/0915

摘要： An ISL clamped NPN transistor and a PNP interface transistor are merged together in a single semiconductive isolation island. The two transistors are laterally separated from each other along a semiconductive surface of the island, which also includes one or more metallic elements forming individual Schottky barrier contact diodes with the semiconductive surface. The PNP transistor provides translation between an ISL logic gate and a TTL logic gate. One of the Schottky diodes may be used in combination with the NPN transistor as an active pulldown for an output transistor of the TTL logic gate.

摘要翻译： 一个ISL钳位NPN晶体管和一个PNP接口晶体管在一个半导体隔离岛中合并在一起。 两个晶体管沿着岛的半导体表面横向分离，该半导体表面还包括形成具有半导体表面的单个肖特基势垒接触二极管的一个或多个金属元件。 PNP晶体管提供ISL逻辑门和TTL逻辑门之间的转换。 其中一个肖特基二极管可以与NPN晶体管组合使用，作为TTL逻辑门的输出晶体管的有源下拉。

公开(公告)号：US4595942A

公开(公告)日：1986-06-17

申请号：US934955

申请日：1978-08-18

申请人： Jan Lohstroh

发明人： Jan Lohstroh

IPC分类号： H01L21/74 ,  H01L21/8222 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/07 ,  H01L27/082 ,  H03K19/091 ,  H01L27/04

CPC分类号： H01L27/0233 ,  H01L27/075 ,  H01L27/0821 ,  H01L27/0826

摘要： A compact integrated logic circuit having an inverter transistor and several coupling diodes adjoining the collector region of said transistor. Current is applied to the base of the transistor which forms the signal input. The inverter transistor has additional means by which an effective complementary auxiliary transistor is incorporated which dissipates a considerable part of the base current in the case the inverter transistor is overdriven so that the charge storage in the inverter transistor is restricted and controlled and by which a Schottky clamp diode across the base-collector junction of the inverter transistor can be avoided.

摘要翻译： 一种紧凑的集成逻辑电路，具有逆变器晶体管和邻接所述晶体管的集电极区域的几个耦合二极管。 电流被施加到形成信号输入的晶体管的基极。 逆变器晶体管具有额外的装置，通过该装置，在逆变器晶体管过驱动的情况下，并入有效的互补辅助晶体管，其消耗相当大的基极电流，使得逆变器晶体管中的电荷存储受到限制和控制，并且通过该方式，肖特基 可以避免跨越逆变器晶体管的基极 - 集电极结的二极管钳位二极管。

公开(公告)号：US4076556A

公开(公告)日：1978-02-28

申请号：US691594

申请日：1976-06-01

申请人： Jorge Agraz-Guerena ,  Alan William Fulton

发明人： Jorge Agraz-Guerena ,  Alan William Fulton

IPC分类号： H01L21/8226 ,  H01L21/331 ,  H01L27/00 ,  H01L27/02 ,  H01L27/07 ,  H01L27/082 ,  H01L29/73 ,  H03K19/091 ,  H01L21/265

CPC分类号： H01L27/0821 ,  H01L27/00 ,  H01L27/0233 ,  H01L27/075 ,  Y10S148/01 ,  Y10S148/085 ,  Y10S148/087

摘要： An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.

摘要翻译： 集成晶体管电路装置提供了在集电极端子处有选择地形成的肖特基二极管和欧姆连接的多集电极晶体管。 在说明性示例中，在覆盖N +衬底的N型外延层中形成垂直晶体管。 P +材料的贯通区域围绕形成有垂直晶体管的外延层的区域。 垂直晶体管的基极通过在与外延层的表面间隔开的位置中注入P型杂质来形成。 得到的基底相对于外延层的表面具有对称的轮廓。 因此，晶体管可以在集电体的表面操作，而不会损害电气操作。 在说明性示例中，使用PNP横向晶体管作为垂直晶体管的电流源。