公开(公告)号：US07187536B2

公开(公告)日：2007-03-06

申请号：US10922459

申请日：2004-08-20

申请人： Francis Edward Hawe

发明人： Francis Edward Hawe

IPC分类号： H01G4/005

CPC分类号： H01G4/228 ,  H01G4/005 ,  H01L23/5223 ,  H01L28/65 ,  H01L28/82 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method are provided for reducing the equivalent series resistance of a capacitor. A capacitor includes one or more conductive interconnections contacting an active region of a first conductive plate of the capacitor at a plurality of locations along a lengthwise direction, such that every portion of the active region of the first conductive plate lies within a maximum distance from one of the locations, the maximum distance being less than the lateral dimension of the active region.

摘要翻译： 提供了一种降低电容器的等效串联电阻的结构和方法。 电容器包括在沿着长度方向的多个位置处接触电容器的第一导电板的有源区的一个或多个导电互连，使得第一导电板的有源区的每个部分位于与一个 的位置，最大距离小于有源区域的横向尺寸。

公开(公告)号：US07187026B2

公开(公告)日：2007-03-06

申请号：US10721082

申请日：2003-11-26

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L27/108

CPC分类号： H01L28/82 ,  H01L21/8221 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor structure formed above the semiconductor substrate and comprising a first electrode, a second electrode provided below the first electrode, a third electrode provided below the second electrode, a first dielectric film provided between the first electrode and the second electrode, and a second dielectric film provided between the second electrode and the third electrode, an insulating film covering the capacitor structure and having a first hole reaching the first electrode, a second hole reaching the second electrode, and a third hole reaching the third electrode, a first conductive connection electrically connecting the first electrode and the third electrode and having portions buried in the first and third holes, and a second conductive connection formed-separately from the first conductive connection and having a portion buried in the second hole.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，形成在半导体衬底上方的电容器结构，包括第一电极，设置在第一电极下方的第二电极，设置在第二电极下方的第三电极，设置在第一电极之间的第一电介质膜 电极和第二电极，以及设置在第二电极和第三电极之间的第二电介质膜，覆盖电容器结构的绝缘膜，具有到达第一电极的第一孔，到达第二电极的第二孔和第三孔 到达第三电极，电连接第一电极和第三电极并且具有埋在第一和第三孔中的部分的第一导电连接，以及与第一导电连接分开形成并具有埋在第二电极中的部分的第二导电连接 孔。

公开(公告)号：US20060263976A1

公开(公告)日：2006-11-23

申请号：US11353923

申请日：2006-02-14

申请人： Shuji Sakamoto

发明人： Shuji Sakamoto

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/82 ,  H01L27/0805 ,  H01L28/86

摘要： A semiconductor device with a capacitor structure for improving area utilization comprises a plurality of electrically conductive layers and a plurality of dielectric layers. The dielectric layers and the electrically conductive layers are alternately superposed one over another, and the electrically conductive layers are alternately electrically connected.

摘要翻译： 具有用于提高面积利用率的电容器结构的半导体器件包括多个导电层和多个电介质层。 电介质层和导电层交替重叠，导电层交替电连接。

公开(公告)号：US20060216902A1

公开(公告)日：2006-09-28

申请号：US11432867

申请日：2006-05-12

申请人： Klaus Schuegraf

发明人： Klaus Schuegraf

IPC分类号： H01L21/44 ,  H01L21/8242

CPC分类号： H01L28/82 ,  H01L21/76886 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/84 ,  H01L28/91 ,  Y10S438/933 ,  Y10S438/964

摘要： Thin film metal-insulator-metal capacitors having enhanced surface area are formed by a substituting metal for silicon in a preformed electrode geometry. The resulting metal structures are advantageous for high-density DRAM applications since they have good conductivity, enhanced surface area and are compatible with capacitor dielectric materials having high dielectric constant.

公开(公告)号：US07112487B2

公开(公告)日：2006-09-26

申请号：US11079131

申请日：2005-03-14

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L21/8242

CPC分类号： H01L27/10817 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/82

摘要： The present invention provides a method for fabricating a stacked capacitor array (1), which comprises a regular arrangement of a plurality of stacked capacitors (2), with a stacked capacitor (2) being at a shorter distance from the respective adjacent stacked capacitor (2) in certain first directions (3) than in certain second directions (4), comprising the following method steps: provision of an auxiliary layer stack (5) having first auxiliary layers (6) with a predetermined etching rate and at least one second auxiliary layer (7) with a higher etching rate on a substrate (8); etching of in each case one hollow cylinder (9) for each stacked capacitor (2) through the auxiliary layer stack (5) in accordance with the regular arrangement, with the auxiliary layer stack (5) being left in place in intermediate regions (10) between the hollow cylinders (9); isotropic etching of the second auxiliary layers (7) to form widened portions (11) of the hollow cylinders (9), without any second auxiliary layer (7) being left in place between in each case two hollow cylinders (9) which adjoin one another in the first direction (3) and with a second residual auxiliary layer (7a) being left in place between in each case two hollow cylinders (9) which adjoin one another in the second direction (4); conformal deposition of an insulator layer (12) in order to completely fill the widened portions (11); deposition of a first electrode layer (13) in the hollow cylinders (9) in order to form the stacked capacitors (2); filling of the hollow cylinders (9) with a first filling (14); removal of the first auxiliary layers (6), the second residual auxiliary layers (7a) and the first filling (14) and completion of the stacked capacitor array (1).

公开(公告)号：US20060208335A1

公开(公告)日：2006-09-21

申请号：US11406186

申请日：2006-04-18

申请人： Kie Ahn ,  Leonard Forbes

发明人： Kie Ahn ,  Leonard Forbes

IPC分类号： H01L29/00

CPC分类号： H01L28/82 ,  C23C14/10 ,  C23C14/226 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02263 ,  H01L21/31695 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstructure formed using a glancing angle deposition (GLAD) process. The microstructure includes columnar structures that provide a porous dielectric material. One aspect is a method of forming a low-k insulator structure. In one embodiment, a predetermined vapor flux incidence angle θ is set with respect to a normal vector for a substrate surface so as to promote a dielectric microstructure with individual columnar structures. Vapor deposition and substrate motion are coordinated so as to form columnar structures in a predetermined shape. Other aspects are provided herein.

公开(公告)号：US20060202250A1

公开(公告)日：2006-09-14

申请号：US11076021

申请日：2005-03-10

申请人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

发明人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

IPC分类号： H01L29/94

CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L28/82

摘要： A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.

摘要翻译： 适用于DRAM单元的存储电容器至少部分地形成在衬底表面之上，并且包括：至少部分地形成在衬底表面上方的存储电极，与存储电极相邻形成的电介质层和形成的对电极 所述对置电极通过所述电介质层与所述存储电极隔离，其中所述存储电极形成为主体，所述主体由平行于所述电介质层的平面中的具有在所述主体外部的曲率中心的至少一个曲面限定 基材表面。 根据另一种结构，存储电极形成为由具有两个相邻平面的至少一组限定的主体，两个平面相对于基板表面垂直延伸，两个平面的法线相交点位于外部 身体。

公开(公告)号：US07060615B2

公开(公告)日：2006-06-13

申请号：US10741256

申请日：2003-12-17

申请人： Eugene P. Marsh

发明人： Eugene P. Marsh

IPC分类号： H01L21/44

CPC分类号： H01G4/005 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53252 ,  H01L28/82 ,  H01L2924/0002 ,  Y10S438/964 ,  H01L2924/00

摘要： A method of forming a roughened layer of platinum, including: a) providing a substrate within a reaction chamber; b) forming an adhesion layer over the substrate; c) flowing an oxidizing gas into the reaction chamber; d) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor onto the adhesion layer in the presence of the oxidizing gas; and e) maintaining a temperature within the reaction chamber at from about 0° C. to less than 300° C. during the depositing.

摘要翻译： 一种形成铂粗糙层的方法，包括：a）在反应室内提供衬底; b）在衬底上形成粘附层; c）将氧化气体流入反应室; d）将铂前体流入反应室，并在氧化气体存在下将铂从铂前体沉积到粘合层上; 和e）在沉积期间将反应室内的温度保持在约0℃至小于300℃。

公开(公告)号：US20060054959A1

公开(公告)日：2006-03-16

申请号：US11223210

申请日：2005-09-12

申请人： Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack

发明人： Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10861 ,  H01L28/82

摘要： A capacitor structure includes: a number of conductive regions of metallic and/or semiconducting materials and/or conductive metal compounds thereof, the conductive regions being arranged as stacked layers in a trench structure of a semiconductor device; and a dielectric surrounding the conductive regions.

摘要翻译： 电容器结构包括：多个金属和/或半导体材料的导电区域和/或其导电金属化合物，所述导电区域被布置为半导体器件的沟槽结构中的堆叠层; 以及围绕导电区域的电介质。

公开(公告)号：US20060017087A1

公开(公告)日：2006-01-26

申请号：US11220058

申请日：2005-09-06

申请人： Masaki Tamaru ,  Toshiyuki Moriwaki ,  Ryoichi Suzuki

发明人： Masaki Tamaru ,  Toshiyuki Moriwaki ,  Ryoichi Suzuki

IPC分类号： H01L29/94

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5223 ,  H01L23/5286 ,  H01L28/40 ,  H01L28/82 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

摘要： A supplemental capacitor is formed using the large capacitance between the wirings (M11 and M12) and that between the through-holes (B11 and B12) because of downsizing of the process technique. The inter-wiring capacitor and inter-through-hole capacitor can be arranged at any optional position within the semiconductor device. The supplemental capacitor can be easily formed in the vicinity of the area where switching noise is generated, thereby effectively realizing the countermeasure for power source noise. In the process technique with advanced downsizing, a capacitor having large capacitance can be formed with a smaller area. In addition, the capacitor can be formed in the same process as the other device such as a transistor without adding any special step.

摘要翻译： 由于处理技术的小型化，使用布线（M 11和M 12）之间的大电容以及通孔（B 11和B 12）之间的大电容形成补充电容器。 布线电容器和通孔间电容器可以布置在半导体器件内的任何可选位置。 补充电容器可以容易地形成在产生开关噪声的区域附近，从而有效地实现了电源噪声的对策。 在具有先进的小型化的工艺技术中，可以形成具有较小电容的电容器，其面积较小。 此外，电容器可以以与其他器件（例如晶体管）相同的工艺形成，而不增加任何特殊的步骤。