公开(公告)号：US20220350568A1

公开(公告)日：2022-11-03

申请号：US17489629

申请日：2021-09-29

申请人： Postech Research and Business Development Foundation

发明人： Seokhyeong KANG ,  Sunmean KIM ,  Sunghye PARK ,  SungYun LEE

IPC分类号： G06F7/502 ,  H03K19/173

摘要： A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.

公开(公告)号：US20220329244A1

公开(公告)日：2022-10-13

申请号：US17835960

申请日：2022-06-09

申请人： iCometrue Company Ltd.

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC分类号： H03K19/1776 ,  H03K19/173 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18 ,  H01L27/11517 ,  H01L27/24 ,  H03K19/17728

摘要： A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

公开(公告)号：US11469911B2

公开(公告)日：2022-10-11

申请号：US16202079

申请日：2018-11-27

申请人： Samsung Electronics Co., Ltd.

发明人： Sompong Paul Olarig

IPC分类号： H04L12/04 ,  H03K19/173 ,  H04L12/44 ,  G06F30/331 ,  G06F13/40 ,  G06F13/38

摘要： A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.

公开(公告)号：US11469722B2

公开(公告)日：2022-10-11

申请号：US16908476

申请日：2020-06-22

申请人： Epirus, Inc.

发明人： Denpol Kultran ,  Yiu Man So ,  Albert Montemuro ,  Jacob Zinn Echoff ,  Michelle Marasigan ,  Michael John Hiatt ,  Jason Reis Chaves ,  Michael Alex Borisov ,  Jar Jueh Lee ,  Harry Bourne Marr, Jr.

IPC分类号： H03F1/07 ,  H03F3/21 ,  H03L7/08 ,  H03K19/173

摘要： Systems and apparatuses are disclosed that include a modular power amplifier having a power amplifier subsystem with a first 90 degree hybrid block configured to receive an RF signal and output a split RF signal with components having a 90 degree phase shift, a second 90 degree hybrid block configured to receive and combine the split RF signal by removing the 90 degree phase shift, a high-power amplifier configured to amplify at least one of the components of the split RF signal. The modular power amplifier also includes a power distribution module configured to regulate an amount of power input to the high-power amplifier and a power sequencer configured to control the timing of power delivery by the power distribution module. Three-dimensional power amplifiers having a first high-power amplifier and a second high-power amplifier having different orientations causing a reduction in electromagnetic interference are also disclosed.

公开(公告)号：US20220317974A1

公开(公告)日：2022-10-06

申请号：US17844169

申请日：2022-06-20

申请人： Imagination Technologies Limited

发明人： Kenneth C. Rovers

IPC分类号： G06F7/544 ,  G06F7/523 ,  G06F9/30 ,  H03K19/00 ,  H03K19/173

摘要： A circuit for use in a processor includes a first processing channel having a first logic unit, a second processing channel having a second logic unit, and multiplexing circuitry. The multiplexing circuitry includes an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.

公开(公告)号：US20220303155A1

公开(公告)日：2022-09-22

申请号：US17832670

申请日：2022-06-05

申请人： KinnexA, Inc.

发明人： Ian CRAYFORD ,  Kuan-Hsiung WEI ,  Shin-Hao CHIEN

IPC分类号： H04L12/40 ,  H04L49/351 ,  G05F1/08 ,  H01R24/64 ,  H02J7/00 ,  H02M3/335 ,  H01L23/467 ,  H03K19/173

摘要： An Ethernet network is composed of one or more network infrastructure devices, such as a hubs, repeaters, switches or routers, which provides data interconnection and may provide operational power, or some part thereof, to remote network data terminal equipment such as a wireless access point, IP telephone, IP camera or network end station. Most Ethernet networks operate over a combination of the pairs in an unshielded twisted pair (UTP) or shielded twisted pair (STP) cable, or in some cases may operate over fiber optic cables. The individual links of Ethernet network, between the network infrastructure device and the Data Terminal Equipment (DTE) may be able to operate at one or more data rates such as 10 Mb/s, 100 Mb/s, 1 Gb/s, 2.5 Gb/s, 5 Gb/s and 10 Gb/s, or any combination thereof. The invention discloses an Ethernet Physical Layer (PHY) circuit, in combination with an Integrated Connector Module (ICM), which may reside inside the network equipment at either end of the Ethernet link. The combined PHY-ICM physical layer network device provides the appropriate encoding/decoding and signaling to operate over the specific network cable medium at the required data rate(s). The electrical and mechanical design of the combined PHY-ICM enables a modular approach such that during final assembly, the PHY-ICM can be optimized for operation over the appropriate data rate(s), whether it supports the provision of operational power between the network equipment, and if so at what power level, as well as other functionality. Furthermore, the PHY-ICM is designed to maintain a common electrical and mechanical footprint regardless of which of the features are included or excluded, to optimize the system cost for a specific maximum data rate, as well as minimize any re-engineering necessary on the part of the network equipment designer.

公开(公告)号：US20220277784A1

公开(公告)日：2022-09-01

申请号：US17746542

申请日：2022-05-17

申请人： Micron Technology, Inc.

发明人： Yuan He ,  Tae H. Kim

IPC分类号： G11C11/4091 ,  G11C5/06 ,  G11C11/4096 ,  G11C11/404 ,  H03K19/173

摘要： A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).

公开(公告)号：US20220269361A1

公开(公告)日：2022-08-25

申请号：US17491501

申请日：2021-09-30

申请人： Teveri LLC

发明人： Gianluca Lazzi ,  Dulce Maria Altabella Lazzi ,  Kyle Loizos

IPC分类号： G06F3/047 ,  H01B1/02 ,  G06F1/16 ,  G06F3/041 ,  H03K19/173

摘要： A touch sensor is provided which includes one or more liquid metal wires and detection circuitry to detect a change in an electrical attribute of the one or more liquid metal cavities based on a depression of the one or more liquid metal cavities, and indicate a touch event corresponding to the depression of the one or more liquid metal cavities based on the change in the electrical attribute.

公开(公告)号：US20220253395A1

公开(公告)日：2022-08-11

申请号：US17169062

申请日：2021-02-05

申请人： SK hynix Inc.

发明人： Lock Duc Nguyen ,  Akshay Ganesh ,  Priyadarsini Lanka ,  Ping Zheng ,  Xiaofang Chen

IPC分类号： G06F13/38 ,  G06F13/40 ,  H03K19/173

摘要： An adaptor device includes a first interface for coupling to a first processor, a second interface for coupling to a second processor, the second interface being different than the first interface, and a plurality of third interfaces, which are different than either the first interface or the second interface. The plurality of third interfaces are configured for coupling to a corresponding plurality of external devices. The adaptor device is configured to receive, at the first interface, a first signal from the first processor. In response to the first signal, the adaptor device couples through the plurality of third interfaces to the plurality of external devices to enable the first processor substantially concurrent access to the plurality of external devices. The adaptor device is also configured to receive, at the first interface, a second signal from the first processor. In response to the second signal, the adaptor device couples the second processor with a selected one of the plurality of external devices.

公开(公告)号：US20220209775A1

公开(公告)日：2022-06-30

申请号：US17699043

申请日：2022-03-18

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu

IPC分类号： H03K19/17728 ,  H03K19/173

摘要： A programmable integrated circuit (“PIC”) device includes configurable logic blocks (“LBs”), routing connections, and configuration memory for performing user defined programmed logic functions. Each configurable LB, in one example, includes a set of lookup tables (“LUTs”) and associated registers. The LUTs, for example, are configured to generate one or more output signals in accordance with a set of input signals. The registers are arranged so that each register corresponds to one LUT. In one embodiment, a group of registers, instead of assigning to a group of LUTs across multiple configurable LBs, is allocated or configured as embedded signature registers in PSD. For example, a first register which corresponds or physically situated in the vicinity of first LUT can be designated as an embedded signature register for storing a fixed value or signature information for facilitating device or IC identification.