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166 条记录 (耗时 0.025 秒)

    Communication system and communication device
    41.
    发明授权
    Communication system and communication device 有权

    公开(公告)号：US10148410B2

    公开(公告)日：2018-12-04

    申请号：US15306364

    申请日：2014-04-25

    申请人： QUADRAC Co., Ltd.

    发明人： Susumu Kusakabe

    IPC分类号： H04L5/22 ,  H04L1/08 ,  H04L5/00 ,  H04L25/493 ,  H04B1/02

    摘要： Provided is a communication system in which one transmission path is shared by a plurality of communication devices, wherein the plurality of communication devices each includes a transmitter that repeatedly transmits one packet to the transmission path with a period of the communication device until a prescribed condition is satisfied, and a receiver that integrates a signal on the transmission path over a period of another communication device until a prescribed condition is satisfied.

    Error detection constants of symbol transition clocking transcoding
    42.
    发明授权
    Error detection constants of symbol transition clocking transcoding 有权

    公开(公告)号：US10089173B2

    公开(公告)日：2018-10-02

    申请号：US14949435

    申请日：2015-11-23

    申请人： QUALCOMM Incorporated

    发明人： Shoichiro Sengoku

    IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/03 ,  H03M5/00 ,  H04L1/00 ,  H04L25/02 ,  H04L25/03 ,  H04L25/14 ,  H04L25/493 ,  H04L27/38 ,  H04L1/24 ,  H04L7/033

    摘要： Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.

    TRANSITION ENFORCING CODING RECEIVER FOR SAMPLING VECTOR SIGNALS WITHOUT USING CLOCK AND DATA RECOVERY
    45.
    发明申请
    TRANSITION ENFORCING CODING RECEIVER FOR SAMPLING VECTOR SIGNALS WITHOUT USING CLOCK AND DATA RECOVERY 有权

    公开(公告)号：US20170126444A1

    公开(公告)日：2017-05-04

    申请号：US15407265

    申请日：2017-01-17

    申请人： MEDIATEK INC.

    发明人： Ching-Hsiang Chang

    IPC分类号： H04L25/493

    CPC分类号： H04L25/493 ,  G06F13/4278 ,  H03L7/0807 ,  H04L25/4917

    摘要： A transition enforcing coding (TEC) receiver includes a delay line circuit, a transition detection circuit, a data sampling circuit, and a skew calibration circuit. The delay line circuit employs a calibrated delay setting to delay a plurality of vector signals to generate a plurality of delayed vector signals under a normal mode, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing, wherein the sampling timing is determined based on an output of the transition detection circuit. The skew calibration circuit sets the calibrated delay setting under a calibration mode, wherein transition skew between different delayed vector signals is reduced by the calibrated delay setting under the normal mode.

    Compact and fast N-factorial single data rate clock and data recovery circuits
    46.
    发明授权
    Compact and fast N-factorial single data rate clock and data recovery circuits 有权
    紧凑，快速的N因子单数据速率时钟和数据恢复电路

    公开(公告)号：US09313058B2

    公开(公告)日：2016-04-12

    申请号：US14459132

    申请日：2014-08-13

    申请人： QUALCOMM Incorporated

    发明人： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee

    IPC分类号： H04B1/00 ,  H04L25/40 ,  H04L7/04 ,  H03L7/00 ,  H04L7/027 ,  H04L7/033 ,  H04L25/493

    CPC分类号： H04L25/40 ,  H03L7/00 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/04 ,  H04L25/14 ,  H04L25/493

    摘要： A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.

    摘要翻译： 多个线路接口被配置为在多个线路接口上接收扩展信号。 扩展信号携带符号，其中连续符号之间保证符号到符号状态转换。 扩展信号由包括第一线路接口上的第一信号的多个转换信号定义。 基于第一信号的第一实例和第一信号的延迟的第二实例之间的比较来提取时钟信号。 基于时钟信号对第一信号的延迟第二实例进行采样以提供符号输出。 时钟提取电路还适于基于多个转换信号之间的第二信号的第一实例与第二信号的延迟的第二实例之间的附加比较来生成时钟信号，其中第一和第二信号是并发的 通过不同线路接口接收的信号。

    SIMULTANEOUS TRANSMISSION OF CLOCK AND BIDIRECTIONAL DATA OVER A COMMUNICATION CHANNEL
    47.
    发明申请
    SIMULTANEOUS TRANSMISSION OF CLOCK AND BIDIRECTIONAL DATA OVER A COMMUNICATION CHANNEL 有权
    通讯通道同时传输时钟和双向数据

    公开(公告)号：US20150270946A1

    公开(公告)日：2015-09-24

    申请号：US14731342

    申请日：2015-06-04

    申请人： Silicon Image, Inc.

    发明人： Inyeol Lee ,  Baegin Sung ,  Hanwoong Sohn ,  Shinje Tahk ,  Sun Woo Baek ,  Chandlee B. Harrell

    IPC分类号： H04L7/00 ,  H04L25/493 ,  H04B3/23 ,  H04L7/04 ,  H04L25/49

    CPC分类号： H04L7/0087 ,  H04B3/23 ,  H04B7/015 ,  H04L7/0278 ,  H04L7/033 ,  H04L7/042 ,  H04L25/4904 ,  H04L25/493

    摘要： Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.

    摘要翻译： 本发明的实施例一般涉及通过通信信道同时传输时钟和双向数据。 发射装置的实施例包括调制器，用于产生包括时钟信号和数据信号的调制信号，时钟信号由调制信号的第一信号边沿调制，数据信号由第二信号的位置调制 调制信号的边缘; 在通信信道上驱动调制信号的驱动器; 回波消除器，用于减去通信信道上的反射信号; 以及数据恢复模块，用于恢复在通信信道上接收到的信号，所述接收信号通过归零（RZ）编码进行编码，该信号与在通信信道上驱动调制信号同时接收。

    Pulsed serial link transmitting data and timing information on a single line
    48.
    发明授权
    Pulsed serial link transmitting data and timing information on a single line 有权
    脉冲串行链路在一条线上发送数据和定时信息

    公开(公告)号：US09118536B2

    公开(公告)日：2015-08-25

    申请号：US11794067

    申请日：2005-12-16

    申请人： Robert G. Warren

    发明人： Robert G. Warren

    IPC分类号： H04L27/00 ,  H04L25/49 ,  H04L25/493

    CPC分类号： H04L25/4902 ,  H04L25/4904 ,  H04L25/493

    摘要： A method of encoding data and timing information on a single line comprising: asserting a first edge on the single line to encode said timing information; asserting a second edge on the single line a selectable time period after said first edge, said selectable time period representing said data, characterized in that: said step of asserting said first edge comprises supplying a clock signal to a clock input of a flip-flop; and the step of asserting the second edge comprises supplying the output of the flip-flop to an input of a programmable delay line having a data input connected to receive said data and an output connected to a reset input of the flip-flop, whereby an output of the flip-flop provides said encoded data and timing information on the single line.

    摘要翻译： 一种在单行上对数据和定时信息进行编码的方法，包括：在单行上声明第一边沿以对所述定时信息进行编码; 在所述第一边缘之后的可选择的时间周期上，在单线上确定第二边沿，所述可选择的时间周期表示所述数据，其特征在于：所述确定所述第一边沿的步骤包括将时钟信号提供给触发器的时钟输入 ; 并且确定第二边沿的步骤包括将触发器的输出提供给具有连接的数据输入的可编程延迟线的输入以接收所述数据，以及连接到触发器的复位输入的输出，由此 触发器的输出在单线上提供所述编码数据和定时信息。

    Electronic circuit
    49.
    发明授权
    Electronic circuit 有权
    电子电路

    公开(公告)号：US08933590B2

    公开(公告)日：2015-01-13

    申请号：US13061128

    申请日：2009-08-04

    申请人： Tadahiro Kuroda

    发明人： Tadahiro Kuroda

    IPC分类号： H03K3/00 ,  H03K3/64 ,  H01F38/00 ,  H01F37/00 ,  H04L25/02 ,  H04L25/493 ,  H04L25/40 ,  H04L25/06

    CPC分类号： H04L25/493 ,  H04L25/0266 ,  H04L25/061 ,  H04L25/40

    摘要： A low-power high-speed asynchronous inductive-coupling transmission and reception technology is provided, in which a current signal of a single pulse is made to flow through a transmitting coil, and a voltage signal of a double pulse induced in an inductively-coupled receiving coil can be received asynchronously. A transmitting circuit for performing non-contact proximity communication adopts a configuration in which current flows through a first coil in a first direction for each change of a logical value of transmit data. A receiving circuit connected to a second coil coupled inductively to the first coil employs a comparator which determines an induced voltage of a double pulse induced in the second coil by current in the first direction and outputs a unipolar single pulse signal. Whenever the single pulse signal outputted by the comparator is inputted, the receiving circuit inverts the output in a sequential circuit and reproduces receive data.

    摘要翻译： 提供了一种低功率高速异步电感耦合传输和接收技术，其中使单个脉冲的电流信号流过发射线圈，并且在感应耦合中感应出双脉冲的电压信号 接收线圈可以异步接收。 用于执行非接触式邻近通信的发送电路采用电流在第一方向上流过第一线圈以对发送数据的逻辑值进行每次改变的配置。 连接到感应地耦合到第一线圈的第二线圈的接收电路采用比较器，该比较器通过在第一方向上的电流来确定在第二线圈中感应的双脉冲的感应电压并输出单极单脉冲信号。 无论何时输入比较器输出的单脉冲信号，接收电路使顺序电路的输出反相，再生接收数据。