公开(公告)号：US6057699A

公开(公告)日：2000-05-02

申请号：US988977

申请日：1997-12-11

Applicant: Rong Yin ,  Mehdi Zamanian

Inventor： Rong Yin ,  Mehdi Zamanian

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2824

Abstract: A frequency test circuit (200) includes a built-in self test (BIST) circuit (212) which provides for testing of a frequency generating circuit such as an oscillator circuit (100). The test circuit (200) includes circuit stages (202-208) which help produce a reference signal (210) which has substantially the same frequency as that produced by the oscillator circuit (100) when it is operational. Since the low current oscillator circuit (100) can fail at any one of the divider or level shifting stages (106-112), the test circuit (200) can determine if the reference signal and the output signal of the oscillator have substantially the same frequency and produce a test condition signal indicative of either a pass or failed test at test port (214).

公开(公告)号：US6052017A

公开(公告)日：2000-04-18

申请号：US928447

申请日：1997-09-12

Applicant: Albino Pidutti ,  Axel Alegre de La Soujeole ,  Elango Pakriswamy

Inventor： Albino Pidutti ,  Axel Alegre de La Soujeole ,  Elango Pakriswamy

IPC: H02P6/08 ,  G11B5/09 ,  G11C5/00 ,  H01L29/00 ,  H02P7/06 ,  H03K17/56 ,  H03K17/74

CPC classification number: H03K17/04106 ,  G11B5/022 ,  H03K17/6872 ,  H03K2217/0045

Abstract: A method and apparatus, for applying a current to a coil of a write head assembly of a disk drive, or the like, to cause the flux within the coil to rapidly reverse, has an H-bridge having two pair of two switchable transistors. Each pair of the transistors is connected between a supply voltage and a reference potential, and is adapted to be connected to the coil between the two transistors of each pair. The two transistors of the first pair may be connected to receive a control signal to turn on complementary transistors of the first and second pair of transistors to selectively control current flow in the coil in first or second directions. A reference current source supplies a reference current, and one of the transistors in each of the first and second pairs of transistors is connected when turned on to mirror the reference current to control the currents in the coil. First and second parallel transistors are connected in parallel respectively with the mirror transistors, the first and second parallel transistors being connected to be turned on respectively by the control signal and the inverted control signal concurrently with the respective mirror transistor. A pair of timing elements turn off respective ones of the parallel transistors after a predetermined time so that when the parallel transistors are turned on, the current in the coil overshoots a value established by the mirror transistors.

Abstract translation: 一种用于将电流施加到盘驱动器等的写入头组件的线圈上以使线圈内的磁通快速反转的方法和装置具有具有两对两个可切换晶体管的H桥。 每对晶体管连接在电源电压和参考电位之间，并且适于连接到每对两​​个晶体管之间的线圈。 第一对的两个晶体管可以被连接以接收控制信号以导通第一和第二对晶体管的互补晶体管，以选择性地控制在第一或第二方向上的线圈中的电流。 参考电流源提供参考电流，并且当导通时连接第一和第二对晶体管中的每个晶体管中的一个晶体管以反映参考电流以控制线圈中的电流。 第一和第二并联晶体管分别与镜晶体管并联连接，第一和第二并联晶体管分别通过控制信号和反相控制信号分别连接到相应的镜像晶体管。 一对定时元件在预定时间之后关闭并联晶体管的各个，使得当并联晶体管导通时，线圈中的电流超过由镜晶体管建立的值。

公开(公告)号：US6046473A

公开(公告)日：2000-04-04

申请号：US905754

申请日：1997-08-04

Applicant: Richard A. Blanchard

Inventor： Richard A. Blanchard

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/7816 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/0847 ,  H01L29/42368

Abstract: A VDMOS structure with an added n- doping component, and a LOCOS oxide self-aligned to it, at tie surface extension of the drain. The additional shallow n- component permits the body diffusion to be heavier, and hence reduces the risk of latchup.

Abstract translation: 具有添加的n-掺杂组分的VDMOS结构和与其排列的连接表面延伸处的与其自对准的LOCOS氧化物。 额外的浅n-成分允许身体扩散更重，因此降低闭锁的风险。

公开(公告)号：US6041000A

公开(公告)日：2000-03-21

申请号：US183840

申请日：1998-10-30

Applicant: David C. McClure ,  Tom Youssef

Inventor： David C. McClure ,  Tom Youssef

IPC: G11C7/20 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/781 ,  G11C7/20

Abstract: A circuit and method are provided for generating an initializing signal to a master enable fuse circuit on a redundant line decoder. An initialization pulse may be applied to a master enable circuit having a master enable fuse. The master enable fuse may be coupled to a switched voltage supply powered selectively by battery voltage and external Vcc. A circuit for generating the INITIAL signal determines the transition from a power down state to a powered state. A series of delay elements in a generating circuit generates a predetermined initialization pulse of around 3 ns to 5 ns. Half-latch circuits may be initialized between a first and second voltage threshold. Accordingly, the master enable circuits may be set to the proper initialization states for proper operation and minimum power consumption.

Abstract translation: 提供一种电路和方法，用于在冗余线路解码器上产生一个初始化信号给主机使能熔丝电路。 可以将初始化脉冲施加到具有主使能熔丝的主启动电路。 主启动保险丝可以耦合到由电池电压和外部Vcc选择性供电的开关电压电源。 用于产生INITIAL信号的电路确定从掉电状态到供电状态的转变。 发生电路中的一系列延迟元件产生约3ns至5ns的预定初始化脉冲。 半锁存电路可以在第一和第二电压阈值之间初始化。 因此，可以将主使能电路设置为适当的初始化状态以进行适当的操作和最小功耗。

公开(公告)号：US6034909A

公开(公告)日：2000-03-07

申请号：US183074

申请日：1998-10-30

Applicant: James Brady

Inventor： James Brady

IPC: G11C7/06 ,  G11C11/4091 ,  G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/06

Abstract: A circuit for controlling isolation transmission gates connected to the bit lines of a dynamic random access memory (DRAM) device. The circuit includes tri-state circuits which selectively configure transmission gate impedance. The transmission gates are configured for low impedance when stored data is provided to the bit lines. The transmission gates are configured for intermediate impedance when the bit lines are driven towards reference voltage levels. Further, the transmission gates are configured for high impedance to isolate the sense amplifiers from blocks of memory cells that are not involved in the execution of an access to a row of memory cells.

Abstract translation: 用于控制连接到动态随机存取存储器（DRAM）设备的位线的隔离传输门的电路。 该电路包括有选择地配置传输门阻抗的三态电路。 当将存储的数据提供给位线时，传输门被配置为低阻抗。 当位线被驱动到参考电压电平时，传输门被配置用于中间阻抗。 此外，传输门被配置用于高阻抗，以将感测放大器与存储器单元的块隔离，所述存储器单元的块不涉及对一行存储器单元的访问的执行。

公开(公告)号：US06028773A

公开(公告)日：2000-02-22

申请号：US971636

申请日：1997-11-17

Applicant: Michael J. Hundt

Inventor： Michael J. Hundt

IPC: G06K9/00 ,  H05K7/02

CPC classification number: G06K9/0002

Abstract: An integrated circuit package for direct mounting of an integrated circuit die to a printed circuit board is disclosed. The integrated circuit die includes a silicon sensor that detects changes in external variables, such as providing an image of a human fingerprint. The integrated circuit die has wire bond pads formed along only one side thereof to provide maximum exposure of the top surface area of the silicon sensor. The die is affixed to the printed circuit board and an adhesive surface coating, such as epoxy, is applied to the die and the printed circuit board for sealing the die thereto. The adhesive surface coating is formed from a first bead applied to the printed circuit board to cover at least the ends of the wires bonded to the board and a second bead applied to the first bead and the die to enclose the sides of the die and partially overlap the wire band pads and wires on top surface thereof.

Abstract translation: 公开了一种用于将集成电路管芯直接安装到印刷电路板的集成电路封装。 集成电路管芯包括硅传感器，其检测外部变量的变化，例如提供人类指纹的图像。 集成电路管芯具有仅沿其一侧形成的引线接合焊盘，以提供硅传感器的顶表面积的最大曝光。 将模具固定到印刷电路板上，并且将诸如环氧树脂的粘合剂表面涂层施加到模具和用于将模具密封的印刷电路板。 粘合剂表面涂层由施加到印刷电路板的第一珠粒形成，以覆盖至少结合到板的引线的端部，以及施加到第一珠粒和模具的第二珠粒以封闭模具的侧面并且部分地 在其顶表面上重叠线带焊盘和电线。

公开(公告)号：US6028635A

公开(公告)日：2000-02-22

申请号：US759166

申请日：1996-12-03

Applicant: Jefferson Eugene Owen ,  Jeyendran Balakrishnan

Inventor： Jefferson Eugene Owen ,  Jeyendran Balakrishnan

IPC: H04N7/30 ,  H03M7/30 ,  H04N7/26 ,  H04N7/50 ,  H04N7/18 ,  H04N7/12 ,  H04N11/04

CPC classification number: H04N19/428 ,  H04N19/423 ,  H04N19/61

Abstract: A method of reducing the memory required for decompression of a compressed frame by storing frames in a compressed format using DCT compression and decoders for implementing such a method are disclosed. The decoder is coupled to a memory where the frame can be stored. The decoder includes a decoder module having a parser, a block decoder module and a motion compensation engine. The decoder module is coupled to a DCT encoder module, which has an output coupled to the memory. The decoder also includes a stored DCT decoder module, which has an input coupled to the memory, a first output coupled to the motion compensation module and a second output that functions as an output of the decoder. In operation, any prediction frames needed for motion compensation decompression of the compressed frame are decompressed in the stored DCT decoder module. The compressed frame is decompressed in the decoder module to obtain a decompressed frame. The decompressed frame is compressed in the DCT encoder module to obtain a recompressed frame. The recompressed frame is then stored in memory. In a DCT based decoder, this is only performed for frames having interpicture prediction errors, such as P and B frames. Frames that do not have interpicture prediction errors, such as I frames can by-pass most of the decoder module, and all of the DCT encoder module. The compressed frame can be stored in the memory without having been decompressed and recompressed.

公开(公告)号：US6011859A

公开(公告)日：2000-01-04

申请号：US887204

申请日：1997-07-02

Applicant: Alexander Kalnitsky ,  Alan Kramer

Inventor： Alexander Kalnitsky ,  Alan Kramer

IPC: A61B5/117 ,  G01B7/28 ,  G06K9/00 ,  G06T1/00 ,  G06T7/00

CPC classification number: G06K9/00053

Abstract: A planar, capacitive-type, rectangular, and multi-pixel fingerprint sensing array is mounted on the horizontal and generally rectangular top-surface of a dome that extends upward generally from the center of a horizontally disposed and generally rectangular silicon substrate member. The dome is formed by four upward extending and inclined, or tapered, side wall surfaces, at least one wall surface of which carries electrical circuit paths that electrically connected to the various circuit elements of the sensing array. A generally rectangular, encircling and wall-like card carrier assembly includes a generally horizontal upper-surface having a generally centered opening through which only the dome and sensing array project upward. The bottom-surface of the card carrier assembly is mounted to edge portions of the silicon substrate member in a manner to surround and protect all but the upward extending dome. A flexible membrane or laminate is sealed to the top-surface of the card carrier assembly to form a flexible surface over the sensing array. The card carrier assembly includes a circuit path having an external portion and having an internal portion that connects to the wall-mounted internal electrical circuit paths, the external portion providing external connection to the internal sensing array.

Abstract translation: 平面的，电容式的，矩形的和多像素的指纹感测阵列安装在圆顶的水平和大致矩形的顶表面上，该圆顶的顶表面一般从水平设置的和大致矩形的硅衬底构件的中心向上延伸。 圆顶由四个向上延伸和倾斜或倾斜的侧壁表面形成，其至少一个壁表面承载电连接到感测阵列的各种电路元件的电路路径。 大致矩形的环绕的壁状卡片托架组件包括具有大致中心的开口的大致水平的上表面，通过该开口仅有圆顶和感测阵列向上突出。 卡片托架组件的底表面以围绕和保护除了向上延伸的圆顶之外的所有的方式安装到硅衬底构件的边缘部分。 柔性膜或层压板被密封到卡片承载组件的顶表面，以在感测阵列上形成柔性表面。 卡片载体组件包括具有外部部分并且具有连接到壁挂式内部电路路径的内部部分的电路，外部部分提供与内部感测阵列的外部连接。

公开(公告)号：US6011298A

公开(公告)日：2000-01-04

申请号：US775632

申请日：1996-12-31

Applicant: Richard A. Blanchard

Inventor： Richard A. Blanchard

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/06 ,  H01L29/732 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/7802 ,  Y10S257/927

Abstract: A semiconductor device structure and method are presented for increasing a breakdown voltage of a junction between a substrate of first conductivity type and a device region. The structure includes a region of second conductivity type in the substrate completely buried in the substrate below and separated from the device region. The region of second conductivity type is located a predetermined distance away from the device region. The distance is sufficient to permit a depletion region to form between the region of second conductivity type and the device region, when a first voltage is applied between the device region and the substrate. The distance also is determined to produce a radius of curvature of the depletion region, when a second voltage that is larger than the first voltage is applied between the device region and the substrate, that is larger than a radius of curvature of the depletion region about the device region that would be formed if the region of second conductivity type were not present. Traditional field shaping regions spaced from the device region at a surface of the substrate and spaced from the region of second conductivity type may be used in conjunction with the buried ring, if desired.

Abstract translation: 提出了一种用于增加第一导电类型的衬底和器件区域之间的结的击穿电压的半导体器件结构和方法。 该结构包括在衬底中完全掩埋在衬底中的第二导电类型的区域，并且与器件区域分离。 第二导电类型的区域位于远离装置区域的预定距离处。 当在器件区域和衬底之间施加第一电压时，该距离足以允许在第二导电类型的区域和器件区域之间形成耗尽区域。 当在器件区域和衬底之间施加大于第一电压的第二电压时，该距离也被确定为产生耗尽区域的曲率半径，该第二电压大于耗尽区域的曲率半径 如果不存在第二导电类型的区域将形成的器件区域。 如果需要，与衬底的表面间隔开并且与第二导电类型的区域间隔开的传统场成形区可以与掩埋环结合使用。

公开(公告)号：US6005296A

公开(公告)日：1999-12-21

申请号：US865641

申请日：1997-05-30

Applicant: Tsiu Chiu Chan

Inventor： Tsiu Chiu Chan

IPC: H01L21/8244 ,  H01L27/11

CPC classification number: H01L27/11 ,  H01L27/1112 ,  Y10S257/903

Abstract: A layout is provided for an SRAM structure. The layout includes a first storage transistor cross-coupled to a second storage transistor to form an SRAM cell. The source regions of the first and second storage transistors are formed in a common region in the substrate to provide a more compact and dense array. The memory cell also includes a first access transistor and a second access transistor appropriately coupled to the appropriate data storage notes. The gate electrodes for the storage transistors and the access transistors are substantially parallel to each other thus providing advantages in operational characteristics and layout efficiencies. The channel regions are also exactly perpendicular to the gate electrodes and are parallel to each other for each of their respective transistors, thereby obtaining similar benefits. The memory cell is designed having a low aspect ratio, preferably lower than 1.2. A single metal line has two contacts to the common source region to ensure grounding of the memory cell at all times and the removal of any stray and parasitic currents which may occur from time to time. The same metal source line is also connected to the P well to ensure that the source region and P well are held at the same voltage at all times and to prevent P well bounce.

Abstract translation: 为SRAM结构提供了布局。 布局包括交叉耦合到第二存储晶体管以形成SRAM单元的第一存储晶体管。 第一和第二存储晶体管的源极区域形成在衬底中的公共区域中以提供更紧凑和致密的阵列。 存储单元还包括适当地耦合到适当的数据存储笔记的第一存取晶体管和第二存取晶体管。 用于存储晶体管和存取晶体管的栅极电极基本上彼此平行，从而提供了操作特性和布局效率方面的优点。 通道区域也完全垂直于栅电极并且对于它们各自的晶体管中的每一个彼此平行，从而获得类似的益处。 存储单元设计成具有低纵横比，优选低于1.2。 单个金属线路具有到共同源极区域的两个触点，以确保存储器单元在任何时间的接地以及消除可能不时发生的任何杂散和寄生电流。 相同的金属源线也连接到P阱，以确保源区和P阱始终保持在相同的电压，并防止P阱反弹。