公开(公告)号：US10462075B2

公开(公告)日：2019-10-29

申请号：US15470940

申请日：2017-03-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Freddy Gabbay ,  Ido Bukshpan ,  Alon Webman ,  Miriam Menes ,  George Elias ,  Noam Katz Abramovich

IPC: H04L12/879 ,  H04L12/861

Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

公开(公告)号：US10444453B1

公开(公告)日：2019-10-15

申请号：US16044520

申请日：2018-07-25

Applicant: Mellanox Technologies, Ltd.

Inventor： Assad Khamaisee ,  Avraham Ganor

IPC: G02B6/42 ,  H04B10/80 ,  H04B10/40

Abstract: An adapter includes an electrical male connector, an electrical female connector, an electronic circuit and one or more visual indicators. The electrical male connector is configured for plugging into a receptacle of a first electro-optical transceiver type having N signal lanes. The electrical female connector is configured to receive a male connector of a second electro-optical transceiver type having M signal lanes, M smaller than N. The electronic circuit is configured to route a partial subset of M signal lanes from among the N signal lanes, between the electrical male connector and the electrical female connector. One or more visual indicators are configured to display a status of one or more network ports mapped to one or more of the signal lanes in the partial subset.

公开(公告)号：US10396527B2

公开(公告)日：2019-08-27

申请号：US15622294

申请日：2017-06-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Alexei Sirbu ,  Vladimir Iakovlev ,  Yuri Berk ,  Itshak Kalifa ,  Elad Mentovich ,  Sylvie Rockman

IPC: H01S5/183 ,  H01S5/20 ,  H01S5/30 ,  H01S5/062 ,  H01S5/343

Abstract: A vertical-cavity surface-emitting laser (VSCEL) and method for producing a VCSEL are described, the VCSEL including an undercut active region. The active region of the VCSEL is undercut relative to current-spreading layers of the VCSEL, such that a width of a tunnel junction of the VCSEL overgrown by a current spreading layer is less than a width of an active region of the VCSEL, and a width of the active region of the VCSEL is less than a width of the overgrown current-spreading layer, such that the VCSEL including the undercut active region is configured to transmit data at speeds greater than 25 gigabits/second.

公开(公告)号：US10394060B2

公开(公告)日：2019-08-27

申请号：US15597835

申请日：2017-05-17

Applicant: Mellanox Technologies, Ltd.

Inventor： Elad Mentovich ,  Sylvie Rockman ,  Jacob Levy ,  Shai Cohen

IPC: G02F1/25 ,  G02F1/025 ,  G01M11/00 ,  G02B6/00 ,  G02F1/015

Abstract: An method for characterizing a modulator for fabricating a silicon photonics circuit and an apparatus (e.g., a silicon photonics wafer) made via the method are described. The method includes determining an absorption spectrum of a modulator and determining, based at least on the determined absorption spectrum, an operational bandwidth of the modulator. The method further includes selecting a laser for coupling with the modulator using the operational bandwidth of the modulator. In this way, the laser is selected such that it has an emission bandwidth that corresponds to the operational bandwidth of the modulator.

公开(公告)号：US10367750B2

公开(公告)日：2019-07-30

申请号：US15790075

申请日：2017-10-23

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi

IPC: H04L29/06 ,  H04L12/891 ,  H04L12/801

Abstract: An apparatus includes an input interface and transmit-side circuitry. The input interface is configured to receive a sequence of packets that carries a stream of video frames. The transmit-side circuitry is configured to divide the sequence of packets into multiple interleaved sub-sequences, wherein each sub-sequence carries a respective sub-stream of the stream of video frames, and wherein at least one of the sub-streams is self-contained and viewable independently of any other sub-stream, and to transmit the multiple sub-sequences of packets to a communication network over respective, different packet flows.

公开(公告)号：US10361777B2

公开(公告)日：2019-07-23

申请号：US15820807

申请日：2017-11-22

Applicant: Mellanox Technologies, Ltd.

Inventor： Elad Mentovich ,  Itsik Kalifa ,  Kfir Margalit

IPC: H04B10/50 ,  H04B10/075

Abstract: A system for testing optical transmitters including a testing unit, a sensor board, one or more support rails, and a driver is provided. The testing board includes sockets that each receive a substrate supporting a plurality of optical transmitters, and the sensor board includes optical receivers. The one or more support rails are attached to one of the testing board or the sensor board and are designed to engage the other of the testing board or the sensor board. The one or more support rails are configured to substantially align each of the optical receivers with a corresponding socket. The driver is in electrical communication with the optical transmitters and the one or more optical receivers such that the driver can apply a current input to at least, one of the optical transmitters and monitor a corresponding output parameter.

公开(公告)号：US20190190892A1

公开(公告)日：2019-06-20

申请号：US15841339

申请日：2017-12-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Adi Menachem ,  Liran Liss ,  Boris Pismenny

IPC: H04L29/06 ,  H04L9/14 ,  H04L9/32 ,  G06F9/455

CPC classification number: H04L63/0428 ,  G06F9/45533 ,  G06F9/45558 ,  G06F21/53 ,  G06F21/602 ,  G06F2009/45587 ,  G06F2009/45595 ,  H04L9/0897 ,  H04L9/14 ,  H04L9/3226 ,  H04L63/0485 ,  H04L63/164 ,  H04L2209/12

Abstract: Computing apparatus includes a host processor, which runs a virtual machine monitor (VMM), which supports a plurality of virtual machines and includes a cryptographic security software module. A network interface controller (NIC) links the host processor to a network so as to transmit and receive data packets from and to the virtual machines and includes a cryptographic security hardware logic module, which when invoked by the VMM, applies the cryptographic security protocol to the data packets while maintaining a state context of the protocol with respect to each of the virtual machines. Upon encountering an exception in applying the cryptographic security protocol, the NIC transfers the data packet, together with the state context of the cryptographic security protocol with respect to the given virtual machine, to the cryptographic security software module for processing.

公开(公告)号：US10320113B2

公开(公告)日：2019-06-11

申请号：US15786222

申请日：2017-10-17

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Nimer Khazen ,  Yaniv Kazav ,  Ayal Shabtay ,  Michal Shlomai ,  Tom David ,  Kfir Katz ,  Oren Weltsch ,  Beeri Halachmi ,  Aziz Mazbar

IPC: H05K7/20 ,  H01R13/518 ,  H01R13/6582 ,  G02B6/44 ,  G02B6/42 ,  H01R13/6592

Abstract: Apparatuses and associated methods of manufacturing are described that provide a cage receptacle assembly configured to receive a cable connector. The cage receptacle assembly includes a cage body defining a first end and a second end. The cage body includes a top cage member attached to a bottom cage member via two side portions of the top cage member, and the bottom cage member defines an opening. The cage receptacle assembly defines a heat dissipation unit disposed within the opening of the bottom cage member, and the heat dissipation unit includes one or more heat dissipation elements allowing heat to be transferred from the cable connector to an external environment of the cage receptacle assembly.

公开(公告)号：US10295740B2

公开(公告)日：2019-05-21

申请号：US15633799

申请日：2017-06-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Ido Bourstein ,  Sylvie Rockman

IPC: G02B6/122 ,  H01S5/022 ,  H01S5/024 ,  G02B6/42 ,  H01S5/042 ,  G02B6/12 ,  H01S5/40

Abstract: An optoelectronic device includes an optoelectronic die, a laser die, and electrical interconnects. The optoelectronic device has a surface. A trench having first and second walls and a floor is formed in the surface, and an electrically conductive layer extends from the floor, via the first wall, to the surface. The laser die includes first and second electrodes and a laser output aperture. The laser die is mounted in the trench and is configured to emit a laser beam. The first electrode is coupled to the electrically conductive layer and the laser output aperture is mechanically aligned with a waveguide that extends from the second wall. The interconnects are formed on the second electrode of the laser die and on selected locations on the surface of the optoelectronic die. The interconnects are coupled to a substrate, and are configured to conduct electrical signals between the optoelectronic die and the substrate.

公开(公告)号：US20190149486A1

公开(公告)日：2019-05-16

申请号：US16181376

申请日：2018-11-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dror Bohrer ,  Noam Bloch ,  Peter Paneah ,  Richard Graham

IPC: H04L12/879 ,  H04L12/883 ,  H04L12/861 ,  H04L12/935

Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.