公开(公告)号：US09305867B1

公开(公告)日：2016-04-05

申请号：US14472108

申请日：2014-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/50 ,  H01L23/34 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An Integrated Circuit device including: a first layer including first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer including second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors and a connection path between the second transistors and the second metal layer, where the connection path includes at least one through-layer via, and where the through-layer via has a diameter less than 150 nm.

Abstract translation: 一种集成电路装置，包括：包括第一晶体管的第一层; 覆盖所述第一晶体管并且提供至少一个到所述第一晶体管的连接的第一金属层; 覆盖所述第一金属层的第二金属层; 以及第二层，包括覆盖所述第二金属层的第二晶体管，其中所述第二金属层被连接以向所述第二晶体管中的至少一个提供功率，以及所述第二晶体管和所述第二金属层之间的连接路径，其中所述连接路径包括 至少一个贯通层通孔，并且其中贯通层通孔具有小于150nm的直径。

公开(公告)号：US09299641B2

公开(公告)日：2016-03-29

申请号：US14747599

申请日：2015-06-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/088 ,  H01L23/367 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device.

Abstract translation: 一种3D设备，包括：包括第一晶体管的第一层，由至少一个互连层覆盖的第一层; 第二层，包括第二晶体管，第二层覆盖互连层; 将所述第二晶体管与所述互连层连接的多个电连接; 以及至少一个导热和非导电接触，其中所述至少一个导热和非导电接触将所述第二层热连接到所述3D器件的顶表面或底表面。

公开(公告)号：US20160035722A1

公开(公告)日：2016-02-04

申请号：US14880276

申请日：2015-10-11

Applicant: MONOLITHIC 3D INC.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/088 ,  H01L29/45

CPC classification number: H01L29/456 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66704 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.

Abstract translation: 一种集成电路器件，包括：包括第一晶体管的第一层; 以及第二层，包括覆盖第一层的第二晶体管，其中第一晶体管面向下并且第二晶体管面向上，并且其中第二层包括直径小于300nm的贯穿层通孔。

公开(公告)号：US08994404B1

公开(公告)日：2015-03-31

申请号：US13796930

申请日：2013-03-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/00 ,  H03K19/096

CPC classification number: H01L27/0688 ,  H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H03K19/096 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 第二层，包括第二晶体管，第二晶体管覆盖第一层互连层; 所述第一层包括第一时钟分配结构，所述第一时钟分配结构包括第一时钟源，所述第二层包括第二时钟分配结构，所述第二时钟分配结构包括第二时钟源，并且所述第二时钟源正在馈送 第一时钟源。

公开(公告)号：US20150054090A1

公开(公告)日：2015-02-26

申请号：US14506160

申请日：2014-10-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L27/115 ,  H01L29/78

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the plurality of second transistors forms a two stable state memory cell including a back-bias region.

Abstract translation: 一种基于3D IC的系统，包括：包括第一晶体管的第一层; 覆盖第一层的第二层，第二层包括多个第二晶体管，其中第二层包括直径小于400nm的至少一个至第二层，并且其中多个第二晶体管中的至少一个 形成包括背偏置区域的两个稳定状态存储单元。

公开(公告)号：US08836073B1

公开(公告)日：2014-09-16

申请号：US13959994

申请日：2013-08-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L27/06 ,  H01L23/544 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An Integrated Circuit device including: a first layer of first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer of second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors.

Abstract translation: 一种集成电路装置，包括：第一层第一晶体管; 覆盖所述第一晶体管并且提供至少一个到所述第一晶体管的连接的第一金属层; 覆盖所述第一金属层的第二金属层; 以及覆盖所述第二金属层的第二层第二晶体管，其中所述第二金属层被连接以向所述第二晶体管中的至少一个提供功率。

公开(公告)号：US08686428B1

公开(公告)日：2014-04-01

申请号：US13678588

申请日：2012-11-16

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/70 ,  H01L21/822

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211

Abstract: A device with an external surface, the device including: a substrate including first mono-crystal transistors; a second layer including second mono-crystal transistors, the second mono-crystal transistors overlaying the first mono-crystal transistors; and a plurality of thermal conduction paths from a plurality of the second layer locations to the external surface, wherein at least one of the thermal conduction paths includes an electrically nonconductive contact.

Abstract translation: 一种具有外表面的器件，该器件包括：包括第一单晶晶体管的衬底; 包括第二单晶晶体管的第二层，覆盖第一单晶晶体管的第二单晶晶体管; 以及从多个第二层位置到外表面的多个热传导路径，其中至少一个导热路径包括非导电接触。

公开(公告)号：US08674470B1

公开(公告)日：2014-03-18

申请号：US13726091

申请日：2012-12-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive layer underneath the second layer, the at least one conductive layer is constructed to provide a back-bias to a portion of the plurality of second single crystal transistors.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 提供所述多个第一晶体管之间的互连的至少一个金属层; 第二层小于2微米厚，第二层包括多个第二单晶晶体管，第二层覆盖至少一个金属层; 以及在所述第二层下面的至少一个导电层，所述至少一个导电层被构造成向所述多个第二单晶晶体管的一部分提供反偏压。

公开(公告)号：US20250142825A1

公开(公告)日：2025-05-01

申请号：US19004160

申请日：2024-12-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another of the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

公开(公告)号：US12250830B2

公开(公告)日：2025-03-11

申请号：US18593727

申请日：2024-03-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, where the memory control circuit includes at least one Look Up Table circuit (“LUT”), and where the device includes a hybrid bonding layer.