公开(公告)号：US20240288680A1

公开(公告)日：2024-08-29

申请号：US18584533

申请日：2024-02-22

Applicant: STMicroelectronics International N.V.

Inventor： Roberto CARMINATI ,  Tarek AFIFI AFIFI ,  Carlo Luigi PRELINI ,  Sonia COSTANTINI

IPC: G02B26/08 ,  G01B7/16 ,  G02B26/10

CPC classification number: G02B26/0833 ,  G01B7/22 ,  G02B26/101

Abstract: A MEMS device includes a semiconductor body with a fixed structure defining a cavity, and a deformable main body suspended on the cavity. A piezoelectric actuator is on the deformable main body, and a piezoelectric sensor element is on the deformable main body, which forms with the deformable main body a strain sensor. The piezoelectric sensor element includes a detection piezoelectric region of aluminum nitride on the deformable main body, and an intermediate detection electrode on the detection piezoelectric region. The deformable main body, the detection piezoelectric region, and the intermediate detection electrode form a first detection capacitor of the strain sensor. The deformable main body, the piezoelectric actuator, and the piezoelectric sensor element form a deformable structure suspended on the cavity and deformable by the piezoelectric actuator, with the strain sensor allowing the deformation of the deformable structure to be detected.

公开(公告)号：US12074605B2

公开(公告)日：2024-08-27

申请号：US18151332

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Aradhana Kumari

IPC: H03K5/1252 ,  H03K5/135

CPC classification number: H03K5/1252 ,  H03K5/135

Abstract: Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.

公开(公告)号：US20240281646A1

公开(公告)日：2024-08-22

申请号：US18192629

申请日：2023-03-29

Applicant: STMicroelectronics International N.V.

Inventor： Michele ROSSI ,  Giuseppe DESOLI ,  Thomas BOESCH

IPC: G06N3/063 ,  G06F17/15 ,  G06F17/16 ,  G06N3/0464

CPC classification number: G06N3/063 ,  G06F17/153 ,  G06F17/16 ,  G06N3/0464

Abstract: A hardware accelerator includes a plurality of functional circuits, a stream switch, and a plurality of stream engines. The stream engines are coupled to the functional circuits via the stream switch, and in operation, generate data streaming requests to stream data to and from the functional circuits. The functional circuits include at least one convolutional cluster, which includes a plurality of processing elements coupled together via a reconfigurable crossbar switch. The reconfigurable crossbar switch is coupled to the stream switch, and in operation, streams data to, from, and between processing elements of the processing cluster.

公开(公告)号：US20240266423A1

公开(公告)日：2024-08-08

申请号：US18420600

申请日：2024-01-23

Applicant: STMicroelectronics International N.V.

Inventor： Benjamin MORILLON

IPC: H01L29/747 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/304

CPC classification number: H01L29/747 ,  H01L21/02323 ,  H01L21/28035 ,  H01L29/66386 ,  H01L21/3043

Abstract: The present disclosure concerns a method of forming an electronic power component inside and on top of a semiconductor substrate, comprising the following successive steps: a) forming of a peripheral groove in the semiconductor substrate on the side of a first surface of the semiconductor substrate; b) deposition of an oxygen-doped polysilicon layer, on top of and in contact with the bottom and the lateral walls of the peripheral groove and with the first surface of the semiconductor substrate; c) local deposition of a glass layer, on the oxygen-doped polysilicon layer, the glass layer extending in the peripheral groove and further extending over a portion of the first surface of the semiconductor substrate; and d) etching of the oxygen-doped polysilicon layer so that it extends on the first surface of the semiconductor substrate beyond the glass layer.

公开(公告)号：US20240264229A1

公开(公告)日：2024-08-08

申请号：US18165602

申请日：2023-02-07

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Mayankkumar Hareshbhai Niranjani ,  Gourav Garg

IPC: G01R31/317 ,  H03K19/0175

CPC classification number: G01R31/31721 ,  H03K19/017509

Abstract: According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input/output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

公开(公告)号：US12055989B2

公开(公告)日：2024-08-06

申请号：US17194037

申请日：2021-03-05

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur Bal ,  Vikas Chelani

IPC: G06F1/24 ,  G06F1/12

CPC classification number: G06F1/24 ,  G06F1/12

Abstract: An integrated circuit includes a plurality of flip-flops and a global reset network for resetting the flip-flops. The integrated circuit includes a synchronous clock delay circuit that delays, responsive to a global reset signal, a transition in a clock signal provided to the flip-flops. The delay in the transition of the clock signal ensures that all of the flip-flops receive the global reset signal within a same delayed clock cycle and that the flip-flops do not receive the global reset signal during a rising or falling edge of the clock signal.

公开(公告)号：US20240258422A1

公开(公告)日：2024-08-01

申请号：US18396524

申请日：2023-12-26

Applicant: STMicroelectronics International N.V.

Inventor： Cateno Marco CAMALLERI ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/66712

Abstract: The present disclosure is directed to a MOSFET device including a semiconductor body with: a plurality of source regions of a first conductivity type; a plurality of body regions of a second conductivity type, which form a plurality of channel regions; and a drain region of the first conductivity type. The MOSFET device further includes a plurality of insulated gate regions, each of which includes a respective gate conductive region and a respective gate dielectric region, which is partially interposed between the gate conductive region and corresponding source regions and is also partially interposed between the gate conductive region and corresponding channel regions. The MOSFET device further includes a plurality of barrier structures, each of which extends on a corresponding insulated gate region and includes at least one respective first barrier region of silicon nitride.

公开(公告)号：US20240258377A1

公开(公告)日：2024-08-01

申请号：US18408474

申请日：2024-01-09

Applicant: STMicroelectronics International N.V.

Inventor： Mario Giuseppe SAGGIO ,  Cateno Marco CAMALLERI ,  Laura Letizia SCALIA ,  Alfio GUARNERA

IPC: H01L29/10 ,  H01L21/04 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1087 ,  H01L21/0465 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: A MOSFET device of a vertical conduction type has a substrate of silicon carbide having a first conductivity type and a main face. A body region of a second conductivity type extends into the substrate from the main face and has a first depth along a first direction. A first and a second source region of the first conductivity type extend inside the body region starting from the main face parallel to each other and have a second depth along the first direction smaller than the first depth and are mutually spaced by a distance in a second direction perpendicular to the first direction. A body contact region of the second conductivity type extends inside the body region between the first and the second source regions and has a third depth along the first direction greater than or equal to the second depth.

公开(公告)号：US20240250058A1

公开(公告)日：2024-07-25

申请号：US18416079

申请日：2024-01-18

Applicant: STMicroelectronics International N.V.

Inventor： Mauro MAZZOLA ,  Fabio MARCHISI

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/40 ,  H01L23/49838 ,  H01L24/35 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/355 ,  H01L2224/40155 ,  H01L2224/48155 ,  H01L2224/73221 ,  H01L2924/153

Abstract: A semiconductor die is arranged at a die mounting location of a substrate. The substrate includes an array of electrically conductive leads at the periphery of the substrate. Electrical coupling is provided between the semiconductor die and selected ones of the electrically conductive leads in the array of electrically conductive leads via electrically conductive ribbons. Each ribbon has a body portion with a first width as well as first and second end portions bonded to the semiconductor die and to the electrically conductive leads, respectively. At least one of the first and second end portions of the electrically conductive ribbon includes a tapered portion having a second width smaller than the first width of the body portion.

公开(公告)号：US20240248864A1

公开(公告)日：2024-07-25

申请号：US18415884

申请日：2024-01-18

Applicant: STMicroelectronics International N.V.

Inventor： Loic PALLARDY ,  Alexandre TORGUE

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A connection circuit couples a first circuit of a device to a bus configured to provide access to an addressable memory space of the device. The connection circuit receives an input address transmitted by the first circuit. The input address corresponds to an address in a first address range or a second address range of the addressable memory space. The addressable memory space further includes a third address range that is not addressable by the first circuit. The connection circuit compares the input address with a threshold address. In response to the comparison, the connection circuit generates a portion of an output address, the output address belonging to the second address range or the third address range of the addressable memory space. The portion of the output address is then supplied to the bus.