公开(公告)号：US6061273A

公开(公告)日：2000-05-09

申请号：US835347

申请日：1997-04-07

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C7/12 ,  G11C7/14 ,  G11C16/24 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C16/24 ,  G11C7/14

Abstract: A pre-charge step determining circuit of a generic bit line, particularly for non-volatile memories, including in one embodiment, circuitry for simulating the selection/deselection of a generic bit line of a memory device; circuitry for simulating the pre-charging of a bit line; and circuitry for determining when the working point of the bit line is reached; the selection/deselection simulation circuitry activating the pre-charging simulation means, which in turn activate the working point attainment determining circuitry, which generate a pre-charge end signal so as to define a minimal duration of the pre-charging that is closely correlated with the characteristics of the actual selection/deselection and pre-charge circuits of the memory device, with the supply conditions, and with the propagation of a generic bit line, the pre-charge simulation circuitry and the working point attainment determining circuitry being activated synchronously with respect to a new reading cycle of the memory device.

Abstract translation: 包括在一个实施例中的通用位线的预充电步骤确定电路，特别是用于非易失性存储器，用于模拟存储器件的通用位线的选择/取消选择的电路; 用于模拟位线预充电的电路; 以及用于确定何时到达位线的工作点的电路; 选择/取消选择模拟电路激活预充电模拟装置，其进而激活工作点达成确定电路，其产生预充电结束信号，以便限定预充电的最小持续时间，其与 存储器件的实际选择/取消选择和预充电电路的特征，具有供应条件，以及通用位线的传播，预充电模拟电路和工作点达成确定电路与 尊重存储器件的新的读取周期。

公开(公告)号：US6040711A

公开(公告)日：2000-03-21

申请号：US670000

申请日：1996-06-26

Applicant: Maria Leena Airaksinen ,  Giorgio Catanzaro

Inventor： Maria Leena Airaksinen ,  Giorgio Catanzaro

IPC: H03K19/0185

CPC classification number: H03K19/0185

Abstract: A CMOS output buffer circuit includes a final amplifier stage having a pull-up transistor and a pull-down transistor connected between a voltage supply and ground and having a common output node, and a control circuitry for driving the final amplifier stage including a first logic gate supplied with an input data signal, the first logic gate driving the pull-up transistor, a second logic gate supplied with said input data signal, the second logic gate driving the pull-down transistor. The pull-up transistor has a bulk electrode connected to a switchable bulk line; an auxiliary circuit is provided which as long as a voltage of the output node is not higher than said supply voltage keeps said switchable bulk line connected to the voltage supply. The first logic gate includes circuitry for transferring the voltage of the output node to said switchable bulk line when the voltage of the output node exceeds the supply voltage.

Abstract translation: CMOS输出缓冲电路包括具有上拉晶体管和连接在电压源和地之间并具有公共输出节点的下拉晶体管的最终放大器级，以及用于驱动最终放大器级的控制电路，包括第一逻辑 栅极，其提供有输入数据信号，驱动上拉晶体管的第一逻辑门，提供有所述输入数据信号的第二逻辑门，驱动下拉晶体管的第二逻辑门。 上拉晶体管具有连接到可切换散装线的体电极; 提供辅助电路，只要输出节点的电压不高于所述电源电压就将所述可切换批量线连接到电压源。 第一逻辑门包括当输出节点的电压超过电源电压时将输出节点的电压传送到所述可切换批量线的电路。

公开(公告)号：USRE36579E

公开(公告)日：2000-02-22

申请号：US488718

申请日：1995-06-08

Applicant: Luigi Pascucci ,  Marco Olivo

Inventor： Luigi Pascucci ,  Marco Olivo

IPC: G11C11/419 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C17/18 ,  G11L13/00

CPC classification number: G11C16/28

Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCC.sub.max. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

Abstract translation: 用于读取EPROM和ROM型存储单元的感测电路采用电路来产生在瞬变期间不受误差的偏移电流，从而允许实现减少的存取时间。 另一方面，感测电路保持电流偏移感测架构的固有优点，其由朝向最大值VCCmax的基本无限的工作电压范围表示。 电流产生电路通过补充的单元行驱动，每行读数被解码，并且在瞬变期间复制为读取选择的行的行为。

公开(公告)号：US6011706A

公开(公告)日：2000-01-04

申请号：US55639

申请日：1998-04-06

Applicant: Claudio Adragna ,  Giuseppe Gattavari ,  Mauro Fagnani

Inventor： Claudio Adragna ,  Giuseppe Gattavari ,  Mauro Fagnani

IPC: H02M3/28 ,  H02M3/335 ,  H04N3/185 ,  H02M1/16 ,  G05F1/40 ,  H01J29/70

CPC classification number: H04N3/185 ,  H02M3/33523

Abstract: The power output of a static DC--DC converter employing a current mode PWM controller is controlled upon the varying of the switching frequency, by detecting the sawtooth signal produced by the local oscillator generating a DC signal with an amplitude inversely proportional to the frequency. The power output is controlled by alternatively clamping the output voltage of the error amplifier of the PWM controller at a voltage proportional to the amplitude of the DC signal, or by offsetting the signal present on the current sensing resistor by a voltage corresponding to the difference between a constant voltage and the DC signal.

Abstract translation: 采用电流模式PWM控制器的静态DC-DC转换器的功率输出通过检测由本地振荡器产生的具有与频率成反比的DC信号产生的锯齿波信号来控制开关频率的变化。 功率输出通过将PWM控制器的误差放大器的输出电压交替钳位在与DC信号的幅度成比例的电压下，或者通过将存在于电流感测电阻器上的信号抵消与 恒定电压和直流信号。

公开(公告)号：US05998855A

公开(公告)日：1999-12-07

申请号：US951686

申请日：1997-10-16

Applicant: Davide Patti

Inventor： Davide Patti

IPC: H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/00 ,  H01L31/11

CPC classification number: H01L29/66303 ,  H01L29/7304

Abstract: A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.

Abstract translation: 具有掩埋P型基极区域的埋入式几何形状的双极型功率晶体管，与发射电极连接的N型发射极区域，P型基极接触区域，N型发射极 - 接触区域和配置在N型连接区域中的N型发射极 - 围绕发射极 - 接触区域。 发射极区域以埋地发射极区域和连接区域限定P型屏幕区域的方式埋在基极区域内。 晶体管还包括与发射电极接触的偏置P型区域，其延伸到屏幕区域。

公开(公告)号：US5994231A

公开(公告)日：1999-11-30

申请号：US996920

申请日：1997-12-23

Applicant: Patrizia Sonego ,  Elio Colabella ,  Maurizio Bacchetta ,  Luca Pividori

Inventor： Patrizia Sonego ,  Elio Colabella ,  Maurizio Bacchetta ,  Luca Pividori

IPC: H01L21/3205 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76819 ,  H01L21/31056 ,  H01L21/316

Abstract: A method of depositing a layered dielectric structure to improve the planarity of electronic devices which include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. The bit lines are isolated from one another by a layered dielectric structure to provide a planar architecture onto which an optional conductive layer may be deposited. The dielectric structure is formed from a highly planarizing dielectric layer of the SOG type spun over a first insulating dielectric layer and solidified by means of a thermal polymerization process. After solidifying the dielectric layer, it is subjected to a rapid thermal annealing treatment.

Abstract translation: 一种沉积层状电介质结构以提高电子器件的平面性的方法，该电子器件包括多个有源元件，这些有源元件具有跨过衬底的栅极区域，作为离散的平行线，例如存储器单元的位线。 位线通过分层电介质结构彼此隔离，以提供可沉积可选导电层的平面结构。 电介质结构由在第一绝缘电介质层上旋转并通过热聚合方法固化的SOG型高平坦化电介质层形成。 固化介电层后，对其进行快速热退火处理。

公开(公告)号：US5990535A

公开(公告)日：1999-11-23

申请号：US634287

申请日：1996-04-18

Applicant: Sergio Palara

Inventor： Sergio Palara

IPC: H01L21/761 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L29/00

CPC classification number: H01L29/7802 ,  H01L21/761 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/1095

Abstract: A power integrated circuit including a substrate of semiconductor material having a first conductivity type on which is formed a first epitaxial layer of the same conductivity type. In a first portion of the first epitaxial layer are formed first and second diffused regions having respectively first and second conductivity type. The first and the second diffused regions are isolated from a power stage included partially in a second portion of the first epitaxial layer by an annular region having the second conductivity type. Over the first epitaxial layer is formed a second epitaxial layer having the first conductivity type in which are extended the first and the second diffused regions to permit forming a control circuitry for the power stage.

Abstract translation: 一种功率集成电路，包括具有第一导电类型的半导体材料的衬底，在其上形成具有相同导电类型的第一外延层。 在第一外延层的第一部分形成有分别具有第一和第二导电类型的第一和第二扩散区域。 第一和第二扩散区域通过具有第二导电类型的环形区域从部分地包括在第一外延层的第二部分中的功率级隔离。 在第一外延层上形成具有第一导电类型的第二外延层，其中延伸第一和第二扩散区域以允许形成用于功率级的控制电路。

公开(公告)号：US5982209A

公开(公告)日：1999-11-09

申请号：US899248

申请日：1997-07-23

Applicant: Antonio Magazzu' ,  Bruno Ferrario

Inventor： Antonio Magazzu' ,  Bruno Ferrario

IPC: G06F1/12 ,  G06F1/10 ,  H03L7/00 ,  H04L7/00 ,  H04L7/033

CPC classification number: G06F1/10 ,  H03L7/00 ,  H04L7/0083 ,  H04L7/033

Abstract: A synchronization circuit for electronic devices and components, being of the type which includes an internal synchronization signal generator and an input/output terminal whereat an external synchronization signal can be received. The synchronization circuit further includes a comparator for receiving both synchronization signals and having a control output for supplying a terminal with the signal corresponding to the master/slave mode of operation of the synchronization circuit. A method of generating and supplying a synchronization signal to a plurality of electronic devices being operated as slave devices to a synchronization circuit acting as the master device is also provided.

Abstract translation: 一种用于电子设备和组件的同步电路，其类型包括内部同步信号发生器和可以接收外部同步信号的输入/输出端子。 同步电路还包括用于接收两个同步信号并具有用于向终端提供与同步电路的主/从操作模式相对应的信号的比较器。 还提供了向作为主设备的同步电路作为从设备操作的多个电子设备产生和提供同步信号的方法。

公开(公告)号：US5959935A

公开(公告)日：1999-09-28

申请号：US865748

申请日：1997-05-30

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C7/22 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C8/18

Abstract: The invention refers to a generating circuit for synchronization signals to regulate the read phase of memory cells in electronic devices with an integrated memory on a semiconductor, of the type controlled by a switching of logical states on a left ATD bus and a right ATD bus and comprising a left and a right section inserted between a first and a second voltage reference and connected respectively to the left and the right ATD bus, the sections being connected at the input to a reference-voltage generated and at the output to an ATD generator. Each of the sections of the generating circuit according to the invention includes a pull-up transistor inserted between the first voltage reference and a first internal circuit node and having a control terminal connected to a polarization structure suitable for modifying the conductivity of pull-up transistors, intentionally reduced in the coupling phase to assure capture of all transitions on the left and right ATD buses, and increased in the operating phase to follow with precision the events of the transition, guiding the read phase in a timely manner.

Abstract translation: 本发明涉及一种用于同步信号的发生电路，用于通过在左ATD总线和右ATD总线上的逻辑状态切换控制的半导体上的集成存储器来调节电子设备中的存储器单元的读取相位， 包括插入在第一和第二电压基准之间并分别连接到左ATD总线和右ATD总线的左部分和右部分，这些部分在输入处连接到产生的参考电压，并在输出端连接到ATD发生器。 根据本发明的发生电路的每个部分包括插入在第一电压基准和第一内部电路节点之间的上拉晶体管，并且具有连接到适于修改上拉晶体管的导电性的偏振结构的控制端子 ，有意减少耦合阶段，以确保捕获左右ATD总线上的所有转换，并在运行阶段增加以跟踪转换事件的精确性，及时指导读取阶段。

公开(公告)号：US5955922A

公开(公告)日：1999-09-21

申请号：US956274

申请日：1997-10-22

Applicant: Germano Nicollini ,  Daniel Senderowicz

Inventor： Germano Nicollini ,  Daniel Senderowicz

IPC: H03F3/45

CPC classification number: H03F3/45192 ,  H03F3/45654 ,  H03F3/45659 ,  H03F2203/45421 ,  H03F2203/45631 ,  H03F2203/45711

Abstract: The circuit of a two-stage fully differential amplifier includes a differential input stage, two output stages and a common mode feedback circuit coupled to the output nodes of the amplifier. The amplifier also includes a non-inverting stage coupled to a respective output node of the differential input stage for driving the respective output stage. Each auxiliary non-inverting stage of the two branches of the fully differential amplifier uses as a biasing current generator, the load device of the branch of the differential input stage to the output of which the non-inverting stage is coupled. The fully differential amplifier permits the use of a null-consumption common mode feedback circuit as normally employed only in a single stage fully differential amplifier.

Abstract translation: 两级全差分放大器的电路包括差分输入级，两个输出级和耦合到放大器的输出节点的共模反馈电路。 放大器还包括非反相级，其耦合到差分输入级的相应输出节点，用于驱动相应的输出级。 全差分放大器的两个分支的每个辅助非反相级用作偏置电流发生器，差分输入级的分支的负载装置到非反相级耦合的输出端。 全差分放大器允许使用通常仅在单级全差分放大器中使用的零消耗共模反馈电路。