公开(公告)号：US20230386566A1

公开(公告)日：2023-11-30

申请号：US18137191

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Harsh RAWAT ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/46

CPC classification number: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/46

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

公开(公告)号：US20230386565A1

公开(公告)日：2023-11-30

申请号：US18136507

申请日：2023-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Harsh RAWAT ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/74

CPC classification number: G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  H03M1/742

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.

公开(公告)号：US11798615B2

公开(公告)日：2023-10-24

申请号：US17721956

申请日：2022-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Tanmoy Roy

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C5/025 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

公开(公告)号：US20230327674A1

公开(公告)日：2023-10-12

申请号：US17719004

申请日：2022-04-12

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Jeena Mary George

IPC: G01R31/3185 ,  H03K3/037 ,  H03K19/00 ,  H03K19/20

CPC classification number: G01R31/318536 ,  H03K3/037 ,  H03K19/0021 ,  H03K19/20 ,  G01R31/318525

Abstract: In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.

公开(公告)号：US20230318287A1

公开(公告)日：2023-10-05

申请号：US18207493

申请日：2023-06-08

Applicant: STMicroelectronics International N.V.

Inventor： Radhakrishnan SITHANANDAM

IPC: H02H9/04 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L27/12 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L29/739 ,  H01L29/87

CPC classification number: H02H9/046 ,  H01L23/528 ,  H01L27/0266 ,  H01L29/0847 ,  H01L27/1203 ,  H01L27/0255 ,  H01L29/7835 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/7391 ,  H01L27/0262 ,  H01L29/87 ,  H01L29/73

Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.

公开(公告)号：US20230317323A1

公开(公告)日：2023-10-05

申请号：US18193387

申请日：2023-03-30

Applicant: STMicroelectronics International N.V.

Inventor： Akshat KUMAR ,  Prashutosh GUPTA

IPC: H01C10/32 ,  H01C10/16 ,  G05B19/042

CPC classification number: H01C10/32 ,  H01C10/16 ,  G05B19/0423

Abstract: An electronic device having a digitally controlled resistor is provided. The digitally controlled resistor includes various switch-resistor segments between voltage nodes. In one embodiment, the switch-resistor segment may include a resistor and a switch coupled parallel to the resistor. In another embodiment, the switch-resistor segment may include a resistor, a complement switch coupled in series with the resistor, and a switch coupled parallel to the resistor and the complement switch. Each switch included in the switch-resistor segment operates based on digital bits. Based on the logic value (either ‘0’ or ‘1’) assigned, the switches turn ON (when logic value is ‘1’) and OFF (when logic value is ‘0’). In some embodiments, the switches and the resistor included in the switch-transistor segment are arranged in a symmetrical manner between voltage nodes.

公开(公告)号：US20230299751A1

公开(公告)日：2023-09-21

申请号：US18185130

申请日：2023-03-16

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Gaurav AGGARWAL

IPC: H03H17/06 ,  H03H17/02

CPC classification number: H03H17/0657 ,  H03H17/0275

Abstract: A method generates a delayed signal based on an input signal, and applies vector magnitude scaling to the delayed signal, generating one or more vector magnitude scaled signals. The input signal is added to the one or more vector magnitude scaled signals, generating one or more phase-shifted signals. Compensation scaling is applied to the one or more phase-shifted signals, generating one or more compensated signals. The input signal and the one or more compensated signals are combined, generating an interpolated output signal. The method may be implemented by a device or a system.

公开(公告)号：US20230282286A1

公开(公告)日：2023-09-07

申请号：US18173472

申请日：2023-02-23

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Marco Bildgen

IPC: G11C16/22 ,  G11C16/16 ,  G06F21/78

CPC classification number: G11C16/22 ,  G11C16/16 ,  G06F21/78 ,  H10B41/30

Abstract: An integrated circuit comprises a memory device including a memory plane having non-volatile memory cells and being non-observable in read mode from outside the memory device, a controller, internal to the memory device, configured to detect the memorized content of the memory plane, and when the memorized content contains locking content, automatically lock any access to the memory plane from outside the memory device, the integrated circuit then being in a locked status, and authorize delivery outside the memory device of at least one sensitive datum stored in the memory plane.

公开(公告)号：US11699995B2

公开(公告)日：2023-07-11

申请号：US17531654

申请日：2021-11-19

Applicant: STMicroelectronics International N.V.

Inventor： Vaibhav Garg ,  Abhishek Jain ,  Anand Kumar

IPC: H03K17/693 ,  H03K17/687 ,  H03K19/017

CPC classification number: H03K17/6872 ,  H03K17/6874 ,  H03K17/693 ,  H03K19/01735

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

公开(公告)号：US20230214292A1

公开(公告)日：2023-07-06

申请号：US17567540

申请日：2022-01-03

Applicant: STMicroelectronics International N.V.

Inventor： Amulya Pandey ,  Manish Bansal ,  Sandeep Bhattacharya

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/27 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/27 ,  G06F9/30145 ,  G06F9/30101 ,  G06F9/4812

Abstract: In an embodiment, an electronic circuit includes: a plurality of signal channels; a signal collection circuit configured to determine an action of the electronic circuit based on channel signals from the plurality of signal channels; and a first signal management circuit coupled between the plurality of signal channels and the signal collection circuit, the first signal management circuit including: a set of internal registers, a set of user registers, and a decoder configured to program the set of internal registers based on a content of the set of user registers, where the first signal management circuit is configured to receive the channel signals via the plurality of signal channels, generate first aggregated signals based on the received channel signals and a content of the set of internal registers, and transmitting the first aggregated signals to the signal collection circuit.