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    Granular clock frequency division using dithering mechanism
    51.
    发明授权
    Granular clock frequency division using dithering mechanism 有权

    公开(公告)号：US11955982B2

    公开(公告)日：2024-04-09

    申请号：US17853323

    申请日：2022-06-29

    Applicant: ATI Technologies ULC

    Inventor： Erwin Chi Wang Pang

    IPC: H03L7/197 ,  H03L7/08 ,  H03L7/081

    CPC classification number: H03L7/1974 ,  H03L7/0805 ,  H03L7/0816

    Abstract: An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.

    Real-time GPU rendering with performance guaranteed power management
    52.
    发明授权
    Real-time GPU rendering with performance guaranteed power management 有权

    公开(公告)号：US11954792B2

    公开(公告)日：2024-04-09

    申请号：US17408034

    申请日：2021-08-20

    Applicant: ATI Technologies ULC

    Inventor： Benjamin Koon Pan Chan ,  William Lloyd Atkinson ,  Clarence Ip ,  Tung Chuen Kwong

    IPC: G06T15/20 ,  G06F15/78 ,  G06T1/20 ,  G09G5/14

    CPC classification number: G06T15/205 ,  G06F15/7814 ,  G06T1/20 ,  G09G5/14 ,  G09G2320/0261

    Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.

    Hybrid render with preferred primitive batch binning and sorting
    53.
    发明授权
    Hybrid render with preferred primitive batch binning and sorting 有权

    公开(公告)号：US11954782B2

    公开(公告)日：2024-04-09

    申请号：US17208730

    申请日：2021-03-22

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio

    IPC: G06T15/00 ,  G06T15/04

    CPC classification number: G06T15/005 ,  G06T15/04

    Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.

    MULTI-PASS WRITEBACK WITH SINGLE-PASS DISPLAY CONSUMPTION
    54.
    发明公开
    MULTI-PASS WRITEBACK WITH SINGLE-PASS DISPLAY CONSUMPTION 审中-公开

    公开(公告)号：US20240112294A1

    公开(公告)日：2024-04-04

    申请号：US17957105

    申请日：2022-09-30

    Applicant: ATI TECHNOLOGIES ULC

    Inventor： Jie Zhou ,  Wing-Chi Chow

    IPC: G06T1/20 ,  G06T1/60 ,  G09G3/20 ,  G09G5/393

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G09G3/2096 ,  G09G5/393 ,  G09G2340/0414 ,  G09G2350/00 ,  G09G2360/12

    Abstract: Techniques described herein allow multi-pass writeback processing of graphical frames (such as those having a high or ultrahigh resolution) to reduce bandwidth for display operations by, for example, splitting an input stream for processing by separate graphical pipelines as two or more spatially segmented portions. After receiving a graphical frame for processing, the graphical frame is spatially segmented into multiple portions. Each of the multiple portions is provided to a respective graphical pipeline of a plurality of graphical pipelines for processing. Each processed portion of the graphical frame is written substantially simultaneously to a corresponding portion of a system memory.

    Selecting a Tiling Scheme for Processing Instances of Input Data Through a Neural Netwok
    55.
    发明公开
    Selecting a Tiling Scheme for Processing Instances of Input Data Through a Neural Netwok 审中-公开

    公开(公告)号：US20240111840A1

    公开(公告)日：2024-04-04

    申请号：US17957508

    申请日：2022-09-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Akila Subramaniam ,  Ying Liu ,  Tung Chuen Kwong ,  Juanjo Noguera

    IPC: G06K9/62 ,  G06N3/04

    CPC classification number: G06K9/6227 ,  G06K9/6261 ,  G06N3/04

    Abstract: An electronic device uses a tiling scheme selected from among a set of tiling schemes for processing instances of input data through a neural network. Each of the tiling schemes is associated with a different arrangement of portions into which instances of input data are divided for processing in the neural network. In operation, processing circuitry in the electronic device acquires information about a neural network and properties of the processing circuitry. The processing circuitry then selects a given tiling scheme from among a set of tiling schemes based on the information. The processing circuitry next processes instances of input data in the neural network using the given tiling scheme. Processing each instance of input data in the neural network includes dividing the instance of input data into portions based on the given tiling scheme, separately processing each of the portions in the neural network, and combining the respective outputs to generate an output for the instance of input data.

    LAST USE CACHE POLICY
    56.
    发明公开
    LAST USE CACHE POLICY 审中-公开

    公开(公告)号：US20240111681A1

    公开(公告)日：2024-04-04

    申请号：US17955888

    申请日：2022-09-29

    Applicant: ATI TECHNOLOGIES ULC

    Inventor： JIMSHED MIRZA

    IPC: G06F12/0877

    CPC classification number: G06F12/0877 ,  G06F2212/60

    Abstract: A processor for implementing a last use cache policy is configured to access data in a portion of a cache, determine that the data in the portion of the cache is no longer needed, and mark the data in the portion of the cache as non-dirty responsive to the determining that the data in the portion of the cache is no longer needed. The marking of the data as non-dirty is indicative that the data in the portion of the cache is not to be evicted from the cache to a memory.

    REMOTE DISPLAY SYNCHRONIZATION TO PRESERVE LOCAL DISPLAY
    58.
    发明公开
    REMOTE DISPLAY SYNCHRONIZATION TO PRESERVE LOCAL DISPLAY 审中-公开

    公开(公告)号：US20240108978A1

    公开(公告)日：2024-04-04

    申请号：US17955651

    申请日：2022-09-29

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Jeffrey G. Cheng ,  Yuping Shen ,  Mikhail Mironov ,  Min Zhang

    IPC: A63F13/355 ,  A63F13/358 ,  H04N19/132

    CPC classification number: A63F13/355 ,  A63F13/358 ,  H04N19/132

    Abstract: A remote display synchronization technique preserves the presence of a local display device for a remotely-rendered video stream. A server and a client device cooperate to dynamically determine a target frame rate for a stream of rendered frames suitable for the current capacities of the server and the client device and networking conditions. The server generates from this target frame rate a synchronization signal that serves as timing control for the rendering process. The client device may provide feedback to instigate a change in the target frame rate, and thus a corresponding change in the synchronization signal. In this approach, the rendering frame rate and the encoding frequency may be “synchronized” in a manner consistent with the capacities of the server, the network, and the client device, resulting in generation, encoding, transmission, decoding, and presentation of a stream of frames that mitigates missed encoding of frames while providing acceptable latency.

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