公开(公告)号：US07491344B2

公开(公告)日：2009-02-17

申请号：US10703947

申请日：2003-11-04

Applicant: Heung-Sik Park ,  Chang-Jin Kang ,  Tae-Hyuk Ahn ,  Kyeong-Koo Chi ,  Sang-Hun Seo

Inventor： Heung-Sik Park ,  Chang-Jin Kang ,  Tae-Hyuk Ahn ,  Kyeong-Koo Chi ,  Sang-Hun Seo

IPC: C23F1/00

CPC classification number: H01J37/32055 ,  H01L21/3065 ,  H01L21/78 ,  H05H1/44

Abstract: Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.

Abstract translation: 本文公开了一种用于蚀刻物体的表面的方法，更具体地，蚀刻硅衬底的背面的方法。 具有硅面的物体被定位成与等离子体产生构件间隔预定间隔距离。 等离子体产生部件产生电弧等离子体以形成等离子体区域。 允许反应气体通过等离子体区域以产生具有高能量和高密度的自由基。 自由基与物体反应以蚀刻物体的表面。 物体的表面可以快速均匀地蚀刻。

公开(公告)号：US20080203590A1

公开(公告)日：2008-08-28

申请号：US12111651

申请日：2008-04-29

Applicant: Chang-Jin KANG ,  Myeong-Cheol KIM ,  Man-Hyoung RYOO ,  Si-Hyeung LEE ,  Doo-Youl LEE

Inventor： Chang-Jin KANG ,  Myeong-Cheol KIM ,  Man-Hyoung RYOO ,  Si-Hyeung LEE ,  Doo-Youl LEE

IPC: H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Abstract translation: 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US20080113511A1

公开(公告)日：2008-05-15

申请号：US11730264

申请日：2007-03-30

Applicant: Sang-joon Park ,  Yong-hyun Kwon ,  Jun Seo ,  Sung-il Cho ,  Chang-jin Kang ,  Jae-kyu Ha

Inventor： Sang-joon Park ,  Yong-hyun Kwon ,  Jun Seo ,  Sung-il Cho ,  Chang-jin Kang ,  Jae-kyu Ha

IPC: H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.

Abstract translation: 公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。 该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案 通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。 然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分 所述材料层形成所述多个接触孔。

公开(公告)号：US20080076071A1

公开(公告)日：2008-03-27

申请号：US11588496

申请日：2006-10-28

Applicant: Seok-Hyun Lim ,  Chang-Jin Kang ,  Gyung-Jin Min ,  Seung-Pil Chung ,  Dong-Seok Lee

Inventor： Seok-Hyun Lim ,  Chang-Jin Kang ,  Gyung-Jin Min ,  Seung-Pil Chung ,  Dong-Seok Lee

IPC: G03F7/00

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816

Abstract: First, second and third layers are formed on a substrate for forming a fine pattern. A first mask pattern having a first space is formed on the third layer. A third layer pattern having a second space exposing the second layer is formed. A first sacrificial layer is formed on the second layer having the third layer pattern. A fourth layer is formed on the first sacrificial layer. A double mask pattern including the first and second mask patterns is formed using the second mask pattern in the second space. A second sacrificial layer is formed on the first sacrificial layer. A sacrificial layer pattern having a third space is formed by removing the double mask pattern, the third layer pattern, and a portion of the first sacrificial layer. An insulation layer pattern is formed by removing a portion of the first and second layers.

Abstract translation: 首先，在用于形成精细图案的基板上形成第二和第三层。 具有第一空间的第一掩模图案形成在第三层上。 形成具有暴露第二层的第二空间的第三层图案。 在具有第三层图案的第二层上形成第一牺牲层。 在第一牺牲层上形成第四层。 使用第二空间中的第二掩模图案形成包括第一和第二掩模图案的双掩模图案。 在第一牺牲层上形成第二牺牲层。 通过去除双掩模图案，第三层图案和第一牺牲层的一部分来形成具有第三空间的牺牲层图案。 通过去除第一层和第二层的一部分来形成绝缘层图案。

公开(公告)号：US07226867B2

公开(公告)日：2007-06-05

申请号：US10419075

申请日：2003-04-21

Applicant: Seung-Young Son ,  Cheol-Kyu Lee ,  Chang-Jin Kang ,  Byeong-Yun Nam

Inventor： Seung-Young Son ,  Cheol-Kyu Lee ,  Chang-Jin Kang ,  Byeong-Yun Nam

IPC: H01L21/302

CPC classification number: C23F4/00 ,  H01L21/32136 ,  H01L21/32139

Abstract: Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cl2 and N2 are provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cl2 and N2 may be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, N2 may be supplied at a flow rate of from 45–65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.

Abstract translation: 提供了蚀刻金属层的方法和使用包括Cl 2 N 2和N 2 N的蚀刻气体的半导体器件的金属化方法。 在金属层上形成掩模层，将蚀刻气体供给到金属层，并使用掩模层作为蚀刻掩模，通过蚀刻气体蚀刻金属层。 金属层可以由铝或铝合金形成。 Cl 2 N 2和N 2可以1:1至1:10的比例混合。 蚀刻气体还可以包括另外的气体，例如包括元素H，O，F，He或C的惰性气体或气体。此外，N 2可以以 蚀刻气体总流量的45-65％，这导致半导体器件中的微负载和锥形缺陷的发生减少。

公开(公告)号：US07052952B2

公开(公告)日：2006-05-30

申请号：US10779494

申请日：2004-02-13

Applicant: In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

Inventor： In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

IPC: H01L21/8242

CPC classification number: H01L27/10885 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/0214 ,  H01L27/10855 ,  Y10S438/978

Abstract: A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

Abstract translation: 通过镶嵌工艺形成导线的方法包括在半导体衬底上形成第一绝缘层，蚀刻第一绝缘层以形成接触孔，并在填充接触孔的第一绝缘层上形成第一导电层。 图案化第一导电层，并且形成填充接触孔并与半导体衬底电连接的存储节点接触。 在存储节点接触件上形成硬掩模，并且使用硬掩模作为蚀刻掩模蚀刻第一绝缘层，以在第一绝缘层中形成沟槽。 在与半导体衬底电连接的沟槽中形成位线。 形成覆盖位线的第二绝缘层。 第二绝缘层和硬掩模被平坦化，并且在存储节点接触件上形成电容器的存储节点。

公开(公告)号：US07001817B2

公开(公告)日：2006-02-21

申请号：US10696417

申请日：2003-10-29

Applicant: Sang-Won Yeo ,  Jeong-Sic Jeon ,  Chang-Jin Kang ,  Chang-Won Lee

Inventor： Sang-Won Yeo ,  Jeong-Sic Jeon ,  Chang-Jin Kang ,  Chang-Won Lee

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28176 ,  H01L29/4941 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating a semiconductor device, including forming a gate insulating film and a gate electrode film on a semiconductor substrate, and patterning the gate electrode film to form a gate electrode. A portion of the gate insulating film is removed to form an undercut region beneath the gate electrode. A buffer silicon film is formed over an entire surface of the resultant substrate to cover the gate electrode and to fill the undercut region. The buffer silicon film is selectively oxidized to form a buffer silicon oxide film.

Abstract translation: 一种制造半导体器件的方法，包括在半导体衬底上形成栅极绝缘膜和栅极电极膜，以及对栅电极膜进行构图以形成栅电极。 去除栅极绝缘膜的一部分以在栅极电极下方形成底切区域。 在所得基板的整个表面上形成缓冲硅膜以覆盖栅电极并填充底切区域。 缓冲硅膜被选择性地氧化以形成缓冲氧化硅膜。

公开(公告)号：US20050158948A1

公开(公告)日：2005-07-21

申请号：US11058670

申请日：2005-02-15

Applicant: Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

Inventor： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

公开(公告)号：US20050130371A1

公开(公告)日：2005-06-16

申请号：US11048995

申请日：2005-02-02

Applicant: Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3213

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

公开(公告)号：US20050112819A1

公开(公告)日：2005-05-26

申请号：US10977385

申请日：2004-10-29

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-II Cho

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-II Cho

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

Abstract translation: 形成电容器结构的方法可以包括在衬底上形成绝缘层，在绝缘层上形成第一电容器电极，在第一电容器电极的部分上形成电容器电介质层，以及在电容器电介质层上形成第二电容器电极， 电容器介电层位于第一和第二电容器电极之间。 更具体地，第一电容器电极可以在其中限定空腔，其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。 还讨论了相关结构。