公开(公告)号：US12040252B2

公开(公告)日：2024-07-16

申请号：US17858660

申请日：2022-07-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Cameron Luce ,  Siva P. Adusumilli ,  Mark Levy

IPC: H01L23/473 ,  H01L21/762 ,  H01L23/367 ,  H01L29/51

CPC classification number: H01L23/473 ,  H01L21/76229 ,  H01L23/367 ,  H01L29/515

Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.

公开(公告)号：US12038615B2

公开(公告)日：2024-07-16

申请号：US17701918

申请日：2022-03-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/42

CPC classification number: G02B6/4203 ,  G02B6/42

Abstract: Structures for an edge coupler and methods of fabricating such structures. The structure includes a substrate, a first waveguide core, and a second waveguide core positioned in a vertical direction between the first waveguide core and the substrate. The second waveguide core includes a taper and an inverse taper longitudinally positioned adjacent to the taper.

公开(公告)号：US20240234533A1

公开(公告)日：2024-07-11

申请号：US18152710

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Shesh Mani Pandey ,  Rajendran Krishnasamy

IPC: H01L29/47 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed is a structure including a substrate and a transistor on the substrate. The transistor includes a barrier layer above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate and a secondary gate. The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions on the barrier layer positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion on the top surface of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the structure.

公开(公告)号：US20240234409A1

公开(公告)日：2024-07-11

申请号：US18152420

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The disclosure provides a structure including an n-type well over an n-type deep well and between a pair of p-type wells for electrostatic discharge (ESD) protection. The structure may include a p-type deep well over a substrate, a first n-type well over the p-type deep well, and a pair of p-type wells over the p-type deep well. The pair of p-type wells are each adjacent opposite horizontal ends of the n-type well. A pair of second n-type wells are over the p-type deep well and adjacent one of the pair of p-type wells. Each p-type well is horizontally between the first n-type well and one of the second n-type wells.

公开(公告)号：US20240224515A1

公开(公告)日：2024-07-04

申请号：US18149733

申请日：2023-01-04

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ralf Richter ,  Stefan Dünkel ,  Violetta Sessi

IPC: H10B41/30

CPC classification number: H10B41/30

Abstract: The disclosure provides a structure with a buried doped region for coupling a source line contact to the gate structure of a memory cell. A structure according to the disclosure includes a memory cell having a gate structure extending in a first lateral direction over a substrate. A buried doped region is within the substrate and extends in a second lateral direction from below the gate structure to a portion of the substrate laterally distal to the gate structure. A source line contact is on the portion of the substrate laterally distal to the gate structure. The buried doped region couples the source line contact to the gate structure of the memory cell through a lower surface of the gate structure.

公开(公告)号：US20240222366A1

公开(公告)日：2024-07-04

申请号：US18604627

申请日：2024-03-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L21/8258 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0605 ,  H01L21/8258 ,  H01L27/0623 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

公开(公告)号：US20240222356A1

公开(公告)日：2024-07-04

申请号：US18149279

申请日：2023-01-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： James P. Mazza ,  Jia Zeng ,  Xuelian Zhu ,  Navneet K. Jain ,  Mahbub Rashed ,  Jacob Mazza

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

公开(公告)号：US12028053B2

公开(公告)日：2024-07-02

申请号：US17643567

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H03K17/10 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/12 ,  H03K17/693

CPC classification number: H03K17/102 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/1203 ,  H03K17/693 ,  H03K2217/0018

Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

公开(公告)号：US12027226B2

公开(公告)日：2024-07-02

申请号：US17810018

申请日：2022-06-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Navneet K. Jain ,  Sven Beyer

IPC: G11C16/04 ,  G11C5/06 ,  G11C11/22 ,  G11C13/00

CPC classification number: G11C5/063 ,  G11C11/22 ,  G11C13/0028 ,  G11C13/0069

Abstract: The structure includes transistors in rows and columns and each having an electric field-based programmable threshold voltage at either a first threshold voltage (VT) or a second VT. The structure further includes first and second signal lines for the rows and columns, respectively. Each first signal line is connected to transistors in a row and each second signal line is connected to transistors in a column. When operated in a switch mode, the transistors may or may not become conductive depending upon their respective VTs. Conductive transistors form connected pairs of first and second signal lines and, thus, create signal paths. The structure can also include mode control circuitry to selectively operate the transistors in either a program mode to set a first VT or an erase mode to set a second VT and to concurrently operate the transistors in the switch mode.

公开(公告)号：US12005389B1

公开(公告)日：2024-06-11

申请号：US18479346

申请日：2023-10-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Justin Weinstein ,  Kimberly E. Konar

IPC: B01D53/04 ,  B01D53/40 ,  B01D53/82 ,  H01L21/67

CPC classification number: B01D53/0446 ,  B01D53/0423 ,  B01D53/40 ,  B01D53/82 ,  B01D2253/102 ,  B01D2258/0216 ,  B01D2259/4145 ,  H01L21/67017

Abstract: A system to abate an emission stream from a semiconductor manufacturing process is disclosed. The system includes a media canister to abate the emission stream in response to an abatement fault in an abatement apparatus. The media canister includes a reaction chamber configured to receive the emission stream in response to the abatement fault, and a dry media disposed within the reaction chamber to abate the emission stream. The dry media includes at least one reactive and/or absorbent material which catalyzes at least one chemical reaction to remove at least one pollutant from the emission stream and yield exhaust substantially free of the at least one pollutant.